US3701984A
Expired / Lapsed
US
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Memory subsystem array
Assignee: RCA Corp
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Filing: 1971-03-05
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Granted: 1972-10-31
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Expires: 1991-03-05
Abstract
Abstract Memory subsystem used with a main storage memory for storing data signals representing blocks of information arranged in words. Digit lines coupled in parallel to all memory subsystems carry block address signals which are compared to associative word signals stored in each memory subsystem. If the block address signals match the associative word signals in one of the memory subsystems, the data signals are retrieved from the memory subsystem containing the matching associative word. If no memory subsystem contains a matching associative word, the information addressed is retrieved from the main storage memory and the data signals and block address signals are transferred to a selected memory subsystem and stored.
Inventors
- 👤 Joseph Richard Burns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:54
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
195 words
In a memory system including addressing means, control means, main storage means and data register means, said addressing means partitioned into a word select portion and a block select portion, at least one memory subsystem comprising the combination of: data storage means for storing data, said means comprising a plurality of elements arranged in rows and columns, each row for storing a data word and each column comprising a digit position; associative word means for storing an address word having a digit corresponding to at least one digit position; word select means responsive to the word select portion of the addressing means for selecting a row storing a data word in all the memory subsystems; transfer means coupled to the digit positions for transferring address words to the associative word means and data words between said data storage means and said data register means; comparator means responsive to the transfer means and the associative word means for providing an output signal which indicates when they are the same; and read out means responsive to said output signal of said comparator means for transferring the data word stored in the selected row to the transfer means.
Claim 2
Dependent Claim
195 words
In a memory system including addressing means, control means, main storage means and data register means, said addressing means partitioned into a word select portion and a block select portion, at least one memory subsystem comprising the combination of: data storage means for storing data, said means comprising a plurality of elements arranged in rows and columns, each row for storing a data word and each column comprising a digit position; associative word means for storing an address word having a digit corresponding to at least one digit position; word select means responsive to the word select portion of the addressing means for selecting a row storing a data word in all the memory subsystems; transfer means coupled to the digit positions for transferring address words to the associative word means and data words between said data storage means and said data register means; comparator means responsive to the transfer means and the associative word means for providing an output signal which indicates when they are the same; and read out means responsive to said output signal of said comparator means for transferring the data word stored in the selected row to the transfer means.
Claim 3
Dependent Claim
55 words
The invention set forth in claim 1 further comprising: write control means for selecting the memory subsystem which is to receive a data word; and write-in means responsive to said control means for transferring data from said main storage means to the data storage means of the memory subsystem indicated by the write control means.
Claim 4
Dependent Claim
94 words
The invention as set forth in claim 2 further comprising: means for causing the addressing means to address successively each word location in a block during a data transfer from the main storage means to the selected memory subsystem whereby each such data transfer causes all the data words in the addressed block in the main storage means to be transferred to the selected data words in the selected memory subsystem; and means for transferring the contents block select portion of the addressing means to the address word means of the selected memory subsystem.
Claim 5
Dependent Claim
33 words
The invention as set forth in claim 3 wherein the write control means is comprised of a shift register in each memory subsystem arranged so that each memory subsystem receives data words cyclically.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-31 | 1976-05-01 | 1976-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-31 | 1980-05-01 | 1980-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-31 | 1984-05-01 | 1984-10-31 | $7700.00 | Window Closed / Lapsed |