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US5055905A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Sony Corp
•
Filing: 1990-10-19
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Granted: 1991-10-08
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Expires: 2010-10-19
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Abstract

Abstract A semiconductor device with a capacitive element of an MIS structure comprising an electrode lead segment and an MIS segment in which an electrode is formed through a dielectric layer on an impurity region over to an aperture in a field insulator film. A high-concentration impurity region which connects the impurity region of the MIS segment to the electrode lead region of the electrode lead segment is formed only in the junction between the impurity region and the electrode lead region. The parasitic capacitance between the capacitive element and the semiconductor substrate is reduced without increasing the parasitic resistance so as to consequently achieve high precision in forming the capacitive element.

Inventors

  • 👤 Hiroaki Anmo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 22:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D84/813

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 141 words
A MIS capacitor comprising: a semiconductor substrate of a first conductivity type: a low-concentration impurity region of opposite conductivity type formed in said substrate; first and second high-concentration impurity regions of opposite conductivity type formed in said low-concentration impurity region, wherein said first and second high-concentration impurity region are laterally spaced from each other; a third high-concentration impurity regions of opposite conductivity type, which extends between the closes adjacent edges of said first and second high-concentration regions and is buried in the bottom of said low-concentration impurity region; a field insulator film having first and second apertures over said first and second high-concentration impurity regions respectively; a dielectric layer formed in said first aperture; a first electrode formed on said dielectric layer over said first aperture; and a second electrode formed on said second high-concentration impurity region over said second aperture.
Claim 2
Dependent Claim 141 words
A MIS capacitor comprising: a semiconductor substrate of a first conductivity type: a low-concentration impurity region of opposite conductivity type formed in said substrate; first and second high-concentration impurity regions of opposite conductivity type formed in said low-concentration impurity region, wherein said first and second high-concentration impurity region are laterally spaced from each other; a third high-concentration impurity regions of opposite conductivity type, which extends between the closes adjacent edges of said first and second high-concentration regions and is buried in the bottom of said low-concentration impurity region; a field insulator film having first and second apertures over said first and second high-concentration impurity regions respectively; a dielectric layer formed in said first aperture; a first electrode formed on said dielectric layer over said first aperture; and a second electrode formed on said second high-concentration impurity region over said second aperture.
Claim 3
Dependent Claim 31 words
A semiconductor device according to claim 1 including a field insulator film formed on said substrate, first and second apertures in said field insulator film for said first and second leads.
Claim 4
Dependent Claim 22 words
A semiconductor device according to claim 2, including a dielectric layer formed over said field insulator film and over said first aperture.
Claim 5
Dependent Claim 23 words
A MIS capacitor according to claim 1, wherein the depth of said first and second high-concentration impurity regions does not reach said substrate.
Claim 6
Dependent Claim 21 words
A MIS capacitor according to claim 1, wherein said low concentration impurity region is the epitaxial layer of opposite conductivity type.
Claim 7
Dependent Claim 137 words
A MIS capacitor comprising: a substrate of a first conductivity type: a low-concentration impurity region of opposite conductivity type formed in said substrate; first and second high-concentration impurity regions of opposite conductivity type formed in said low-concentration impurity region, wherein said first and second high-concentration impurity region are laterally spaced from each other; a third high-concentration impurity regions of opposite conductivity type adjacent the surface of said low-concentration impurity region, which extends between the closest adjacent edges of said first and second high-concentration regions; a field insulator film having first and second apertures over said first and second high-concentration impurity regions respectively; a dielectric layer formed in said first aperture; a first electrode formed on said dielectric layer over said first aperture; and a second electrode formed on said second high-concentration impurity region over said second aperture.
Claim 8
Dependent Claim 137 words
A MIS capacitor comprising: a substrate of a first conductivity type: a low-concentration impurity region of opposite conductivity type formed in said substrate; first and second high-concentration impurity regions of opposite conductivity type formed in said low-concentration impurity region, wherein said first and second high-concentration impurity region are laterally spaced from each other; a third high-concentration impurity regions of opposite conductivity type adjacent the surface of said low-concentration impurity region, which extends between the closest adjacent edges of said first and second high-concentration regions; a field insulator film having first and second apertures over said first and second high-concentration impurity regions respectively; a dielectric layer formed in said first aperture; a first electrode formed on said dielectric layer over said first aperture; and a second electrode formed on said second high-concentration impurity region over said second aperture.
Claim 9
Dependent Claim 22 words
A semiconductor device according to claim 6 including a dielectric layer formed over said field insulator film and over said first aperture.
Claim 10
Dependent Claim 23 words
A MIS capacitor according to claim 6, wherein the depth of said first and second high-concentration impurity regions does not reach said substrate.
Claim 11
Dependent Claim 21 words
A MIS capacitor according to claim 6, wherein said low concentration impurity region is the epitaxial layer of opposite conductivity type.
Claim 12
Dependent Claim 21 words
A MIS capacitor according to claim 6, wherein said low concentration impurity region is the well region formed in said substrate.

References Cited (Backward Citations)

US4686557A Cited
US4887135A Cited
US4805071A Cited
US4933739A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-07 1995-04-08 1995-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-07 1999-04-08 1999-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-07 2003-04-08 2003-10-08 $7700.00 Window Closed / Lapsed

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