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US4686557A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor element and method for producing the same

Assignee: Siemens AG
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Filing: 1984-12-28
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Granted: 1987-08-11
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Expires: 2004-12-28
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Abstract

Abstract Semiconductor element, including at least one bi-polar power transistor having parallel-connected transistor regions, active and contacted partial base zone regions, an emitter zone-base zone pn-junction, and base barrier resistances disposed between the active base regions at the emitter-base pn-junction and the contacted base regions, the greater part of the base current being conducted through the base barrier resistances and the voltage drop over the emitter region being small compared to the voltage between the active base region and the contacted base region.

Inventors

  • 👤 Peter Mahrla

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 03:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 233 words
Integrated bipolar power transistor arrangement including a plurality of parallel connected bipolar partial power transistors comprising: an epitaxial layer provided on a semiconductor substrate and forming contact connected collector regions for said partial power transistors, a buried layer region for said collector regions provided at the interface between said semiconductor substrate and said epitaxial layer; deep diffused collector contact regions projecting downward from the surface facing away from the substrate of the epitaxial layer into the buried layer, the contact connected collector region having an upper surface and being bounded by the buried layer and the collector contact regions; further comprising a common base region formed in the upper surface of the collector region including an inner contact-connected base region and an annular base region disposed around and concentrically with the inner base region, an annular emitter region disposed in said base region inside and concentrically with said annular base region, an annular barrier region formed in said base region inside said annular emitter region separating said inner base region and said annular base region, said barrier region extending downward partially into the base region, and annular barrier base-pinch resistance being formed by a space between the lower surface of said annular barrier region and the boundary between the collector region and the base region, said annular barrier resistance forming a connection between the inner contact-connected base zone and the annular base region.
Claim 2
Dependent Claim 233 words
Integrated bipolar power transistor arrangement including a plurality of parallel connected bipolar partial power transistors comprising: an epitaxial layer provided on a semiconductor substrate and forming contact connected collector regions for said partial power transistors, a buried layer region for said collector regions provided at the interface between said semiconductor substrate and said epitaxial layer; deep diffused collector contact regions projecting downward from the surface facing away from the substrate of the epitaxial layer into the buried layer, the contact connected collector region having an upper surface and being bounded by the buried layer and the collector contact regions; further comprising a common base region formed in the upper surface of the collector region including an inner contact-connected base region and an annular base region disposed around and concentrically with the inner base region, an annular emitter region disposed in said base region inside and concentrically with said annular base region, an annular barrier region formed in said base region inside said annular emitter region separating said inner base region and said annular base region, said barrier region extending downward partially into the base region, and annular barrier base-pinch resistance being formed by a space between the lower surface of said annular barrier region and the boundary between the collector region and the base region, said annular barrier resistance forming a connection between the inner contact-connected base zone and the annular base region.
Claim 3
Dependent Claim 20 words
Power transistor according to claim 1 wherein said annular barrier base-pinch resistivity has an area resistance of approximately 5 kilo-ohm/square.
Claim 4
Dependent Claim 183 words
Integrated bipolar power transistor arrangement including a plurality of parallel connected bipolar partial power transistors comprising: an epitaxial layer provided on a semiconductor substrate and forming contact connected collector regions for said partial power transistors, a buried layer region for said collector regions provided at the interface between said cemiconductor substrate and said epitaxial layer; deep diffused collector contact regions projecting downward from the surface of the epitaxial layer into the buried layer, the contact connected collector region having an upper surface and being bounded by the buried layer and the collector contact regions, comprising a common base region formed in the upper surface of the collector region, consisting of an inner contact-connected base region and a semi-toroid-shaped annular base region disposed around and concentrically with the inner base region, an annular emitter region disposed in said base region inside and concentrically with said annular base region, said annular base region completely enclosing said annular emitter region; an annular disc-shaped barrier resistance embedded in the upper surface of the base region, disposed between the annular base region and the inner contact-connected base region.
Claim 5
Dependent Claim 183 words
Integrated bipolar power transistor arrangement including a plurality of parallel connected bipolar partial power transistors comprising: an epitaxial layer provided on a semiconductor substrate and forming contact connected collector regions for said partial power transistors, a buried layer region for said collector regions provided at the interface between said cemiconductor substrate and said epitaxial layer; deep diffused collector contact regions projecting downward from the surface of the epitaxial layer into the buried layer, the contact connected collector region having an upper surface and being bounded by the buried layer and the collector contact regions, comprising a common base region formed in the upper surface of the collector region, consisting of an inner contact-connected base region and a semi-toroid-shaped annular base region disposed around and concentrically with the inner base region, an annular emitter region disposed in said base region inside and concentrically with said annular base region, said annular base region completely enclosing said annular emitter region; an annular disc-shaped barrier resistance embedded in the upper surface of the base region, disposed between the annular base region and the inner contact-connected base region.
Claim 6
Dependent Claim 19 words
Power transistor according to claim 3 wherein said disc-shaped barrier resistivity has a resistance value of approximately 2 kilo-ohm/square.
Claim 7
Dependent Claim 16 words
Power transistor according to claim 4 wherein said disc-shaped barrier resistance is an implanted high-ohmic resistance.

References Cited (Backward Citations)

US3665266A Cited
US3858234A Cited
US4511912A Cited
US4486770A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-08-10 1991-02-09 1991-08-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-08-10 1995-02-09 1995-08-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-08-10 1999-02-09 1999-08-11 $7700.00 Window Closed / Lapsed

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