Programmable logic array having feedback flip-flops connected between a product array's inputs and its outputs

Claim 2

A programmable logic device comprising: a plurality of flip-flop circuits; a logical product matrix including logical product term lines which intersect inverted output lines and non-inverted output lines of said flip-flop circuits; and a group of wiring lines for connecting outputs produced from a part of said logical product term lines to input contacts of said flip-flop circuits; wherein a sequential logic circuit is formed by programmably connecting lattice points of said logical product matrix and feeding-back signals produced in the logical product term lines pertaining to said programmed lattice points to input contacts of a circuit block including said flip-flop circuits through said group of wiring lines.

Claim 3

The programmable logic device according to claim 1, wherein said group of wiring lines connect logical product (AND) outputs produced from a part of said logical product term lines to input contacts of said flip-flop circuits.

Claim 4

The programmable logic device according to claim 1, wherein said group of wiring lines connected inverted logical product (NAND) outputs from a part of said logical product term lines to input contacts of said flip-flop circuits.

Claim 5

The programmable logic device according to claim 1, wherein the outputs produced from a part of said logical product term lines are directly connected to input contacts of said flip-flop circuits.

Claim 6

The programmable logic device according to claim 1, wherein each of said plurality of flip-flop circuits is a T-type flip-flop circuit.

Claim 7

A programmable logic device for forming a desired logic circuit by programming lattice points of logical product term lines, comprising: a plurality of flip-flop circuits; a first logical product matrix having at least a group of input signal lines supplied with outputs of said flip-flop circuits, and a group of logical product term lines intersecting said group of input signal lines; a second logical product matrix having a group of input signal lines supplied with logical product outputs produced by programmably determining logical product term lines of said first logical product matrix, and a group of logical product term lines intersecting said group of input signal lines; a group of wiring lines for supplying logical product outputs produced by programmably determining other logical product term lines of said first logical product matrix to suitable input contacts of said flip-flop circuits; and a group of wiring lines for supplying logical product outputs produced by programmably determining said logical product term lines of said second logical product matrix to reset signal input contacts of said flip-flop circuits.

Claim 8

A programmable logic device for forming a desired logic circuit by programming lattice points of logical product term lines, comprising: a plurality of flip-flop circuits; a first logical product matrix having at least a group of input signal lines supplied with outputs of said flip-flop circuits, and a group of logical product term lines intersecting said group of input signal lines; a second logical product matrix having a group of input signal lines supplied with logical product outputs produced by programmably determining logical product term lines of said first logical product matrix, and a group of logical product term lines intersecting said group of input signal lines; a group of wiring lines for supplying logical product outputs produced by programmably determining other logical product term lines of said first logical product matrix to suitable input contacts of said flip-flop circuits; and a group of wiring lines for supplying logical product outputs produced by programmably determining said logical product term lines of said second logical product matrix to reset signal input contacts of said flip-flop circuits.

Claim 9

A programmable logic device for forming a desired logic circuit by programming lattice points of logical product term lines, comprising: a plurality of counters; a first logical product matrix having at least a group of input signal lines supplied with outputs of said counters, and a group of logical product term lines intersecting said group of input signal lines; a second logical product matrix having a group of input signal lines supplied with logical product outputs produced by programmably determining logical product term lines of said first logical product matrix, and a group of logical product term lines intersecting said group of input signal lines; a group of wiring lines for supplying logical product outputs produced by programmably determining other logical product term lines of said first logical product matrix to suitable input contacts of said counters; and a group of wiring lines for supplying logical product outputs produced by programmably determining said logical product term lines of said second logical product matrix to reset signal input contacts of said counters.

Claim 10

A programmable logic device for forming a desired logic circuit by programming lattice points of logical product term lines, comprising: a plurality of counters; a first logical product matrix having at least a group of input signal lines supplied with outputs of said counters, and a group of logical product term lines intersecting said group of input signal lines; a second logical product matrix having a group of input signal lines supplied with logical product outputs produced by programmably determining logical product term lines of said first logical product matrix, and a group of logical product term lines intersecting said group of input signal lines; a group of wiring lines for supplying logical product outputs produced by programmably determining other logical product term lines of said first logical product matrix to suitable input contacts of said counters; and a group of wiring lines for supplying logical product outputs produced by programmably determining said logical product term lines of said second logical product matrix to reset signal input contacts of said counters.

Claim 11

A programmable logic device comprising: first through n cascade-connected flip-flop circuits; a programmable logical product matrix including logical product term lines which intersect inverted output lines and non-inverted output lines of said flip-flop circuits; and a group of wiring lines by which suitable signals produced in said logical product term lines are programmably connected so as to be fed back to an input contact of said first flip-flop circuit.

Claim 12

A programmable logic device comprising: first through n cascade-connected flip-flop circuits; a programmable logical product matrix including logical product term lines which intersect inverted output lines and non-inverted output lines of said flip-flop circuits; and a group of wiring lines by which suitable signals produced in said logical product term lines are programmably connected so as to be fed back to an input contact of said first flip-flop circuit.

Claim 13

The programmable logic device according to claim 8, further comprising a buffer circuit connected to the input contact of said first flip-flop circuit.

Claim 14

The programmable logic device according to claim 8, further comprising logical gate means connected to the input contact of said first flip-flop circuit.

Claim 15

The programmable logic device according to claim 8, further comprising a plurality of AND gates, and wherein said first flip-flop circuit is a JK-type flip-flop circuit having a J-input contact and a K-input contact, one of said AND gates being connected to the J-input contact and a different one of said AND gates being connected to the K-input contact.