Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device having at least one capacitor, comprising: a first semiconductor layer of a first conductivity type having a relatively high impurity concentration in a range of 1×10 16 through 1×10 21 /cm 3 ; a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of 1×10 14 through 1×10 16 /cm 3 ; a groove having sidewall surface areas extending through said second semiconductor layer and into said first semiconductor layer; an oxide layer formed on said sidewall surface areas of said groove; a capacitor electrode in said groove bounded by said oxide layer lining said groove; and a third semiconductor layer of a second conductivity type surrounding said groove and a depletion layer surrounding said third semiconductor layer; wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by the depletion layer between said third semiconductor layer and said second semiconductor layer.

Claim 3

A semiconductor integrated circuit device in accordance with claim 1, wherein said device includes memory cells each having a single transistor and a single capacitor.

Claim 4

A semiconductor integrated circuit device having at least one capacitor, comprising: a first semiconductor layer of a first conductivity type having a relatively high impurity concentration in a range of 1×10 16 through 1×10 21 /cm 3 ; a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of 1×10 14 through 1×10 16 /cm 3 ; a groove having sidewall surface areas extending perpendicular to the plane of an interface of said first and second semiconductor layers, an oxide layer formed on said sidewall surface areas of said groove; a capacitor electrode in said groove bounded by said oxide layer lining said groove; and a third semiconductor layer of a second conductivity type surrounding said groove and a depletion layer surrounding said third semiconductor layer, said depletion layer being narrower in a portion proximate said first semiconductor layer than in a portion proximate said second semiconductor layer; wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by said the depletion layer between said third semiconductor layer and said second semiconductor layer.

Claim 5

A semiconductor integrated circuit device having at least one capacitor, comprising: a first semiconductor layer of a first conductivity type having a relatively high impurity concentration in a range of 1×10 16 through 1×10 21 /cm 3 ; a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of 1×10 14 through 1×10 16 /cm 3 ; a groove having sidewall surface areas extending perpendicular to the plane of an interface of said first and second semiconductor layers, an oxide layer formed on said sidewall surface areas of said groove; a capacitor electrode in said groove bounded by said oxide layer lining said groove; and a third semiconductor layer of a second conductivity type surrounding said groove and a depletion layer surrounding said third semiconductor layer, said depletion layer being narrower in a portion proximate said first semiconductor layer than in a portion proximate said second semiconductor layer; wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by said the depletion layer between said third semiconductor layer and said second semiconductor layer.

Claim 6

A semiconductor integrated circuit device in accordance with claim 3, wherein said device includes memory cells each having a single transistor and a single capacitor.

Claim 7

A semiconductor integrated circuit device having at least one capacitor, comprising: a first semiconductor layer of a first conductivity type having a relatively high impurity concentration of in a range of 1×10 16 through 1×10 21 /cm 3 ; a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of in a range of 1×10 14 through 1×10 16 /cm 3 ; a groove having sidewall surface areas extending through said second semiconductor layer and into said first semiconductor layer; an oxide layer formed on said sidewall surface areas of said groove; a capacitor electrode in said groove bounded by said oxide layer lining said groove; and a third semiconductor layer of a second conductivity type, formed in response to the application of a relatively high voltage to said capacitor electrode, surrounding said groove and a depletion layer surrounding said third semiconductor layer.

Claim 8

A semiconductor integrated circuit device having at least one capacitor, comprising: a first semiconductor layer of a first conductivity type having a relatively high impurity concentration of in a range of 1×10 16 through 1×10 21 /cm 3 ; a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of in a range of 1×10 14 through 1×10 16 /cm 3 ; a groove having sidewall surface areas extending through said second semiconductor layer and into said first semiconductor layer; an oxide layer formed on said sidewall surface areas of said groove; a capacitor electrode in said groove bounded by said oxide layer lining said groove; and a third semiconductor layer of a second conductivity type, formed in response to the application of a relatively high voltage to said capacitor electrode, surrounding said groove and a depletion layer surrounding said third semiconductor layer.

Claim 9

A semiconductor integrated circuit device in accordance with claim 5 wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by said the depletion layer between said third semiconductor layer and said second semiconductor layer.

Claim 10

A semiconductor integrated circuit device in accordance with claim 6, wherein said device includes memory cells each having a single transistor and a single capacitor.