US5047711A — Wafer-level burn-in testing of integrated circuits

Claim 1

Independent Claim 70 words

A wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die; and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer.

Claim 2

Dependent Claim 70 words

A wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die; and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer.

Claim 3

Dependent Claim 102 words

A wafer according to claim 1, in which the scribe lines are disposed parallel and perpendicular to one another to define an array of rectangular integrated circuits, wherein a first set of said contact pads extend into said scribe lanes from areas of the integrated circuits near the intersections of the scribe lines for use in providing test stimulus signals during said testing; and wherein a second set of said contact pads extend into the scribe lanes from areas of the integrated circuits outside the intersections of the scribe lines for use in providing power to the integrated circuits during said testing.

Claim 4

Independent Claim 136 words

A system for testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the system comprising testing means for simultaneously applying and separately monitoring burn-in test signals for individual integrated circuits; and contact means for coupling said testing means to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for a plurality of said individual integrated circuits while they are contained in the wafer.

Claim 5

Independent Claim 136 words

A system for testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the system comprising testing means for simultaneously applying and separately monitoring burn-in test signals for individual integrated circuits; and contact means for coupling said testing means to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for a plurality of said individual integrated circuits while they are contained in the wafer.

Claim 6

Dependent Claim 50 words

A system according to claim 3, further comprising control means coupled to said testing means for discontinuing the application of burn-in test signals to a given individual integrated circuit when said monitored test signals for said given integrated circuit indicate that said given integrated circuit has failed the burn-in test.

Claim 7

Dependent Claim 99 words

A system according to claim 3, for testing a wafer in which the scribe lines are disposed parallel and perpendicular to one another to define an array of rectangular integrated circuits, and in which first sets of said contact pads extend into said scribe lanes from areas of the integrated circuits near the intersections of the scribe lines, wherein the contact means include clusters of probes for contacting the first sets of contact pads in those areas of the wafer near the intersections of the scribe lines for providing test stimulus signals to the integrated circuits during said testing.

Claim 8

Dependent Claim 74 words

A system according to claim 5, for testing a wafer in which second sets of said contact pads extend into said scribe lanes from areas of the integrated circuits outside the intersections of the scribe lines, wherein the contact means further include probes for contacting the second sets of contact pads in those areas of the wafer outside the intersections of the scribe lines for providing power to the integrated circuits during said testing.

Claim 9

Dependent Claim 75 words

A system according to claim 3, further comprising means for sensing the temperature of the wafer during said testing; cooling means for receiving the wafer during said testing; and control means coupled to said sensing means, said cooling means and the testing means for controlling the temperature of wafer during said testing by controlling said cooling means, varying said power, and/or varying said test stimulus signals in accordance with the sensed temperature of the wafer.

Claim 10

Independent Claim 171 words

A method of testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the method comprising the steps of (a) coupling testing means for applying and monitoring burn-in test signals for individual integrated circuits to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for said plurality of individual integrated circuits while they are contained in the wafer; (b) simultaneously applying burn-in test signals to the coupled plurality of individual integrated circuits while they are contained in the wafer; and (c) separately monitoring burn-in test signals for the coupled individual integrated circuits while they are contained in the wafer.

Claim 11

Independent Claim 171 words

A method of testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the method comprising the steps of (a) coupling testing means for applying and monitoring burn-in test signals for individual integrated circuits to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for said plurality of individual integrated circuits while they are contained in the wafer; (b) simultaneously applying burn-in test signals to the coupled plurality of individual integrated circuits while they are contained in the wafer; and (c) separately monitoring burn-in test signals for the coupled individual integrated circuits while they are contained in the wafer.

Claim 12

Dependent Claim 46 words

A method according to claim 8 further comprising the step of (d) discontinuing the application of burn-in test signals to a given individual integrated circuit when said monitored test signals for said given integrated circuit indicate that said given integrated circuit has failed the burn-in test.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-09-09	1995-03-11	1995-09-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-09-09	1999-03-11	1999-09-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-09-09	2003-03-11	2003-09-10	$7700.00	Window Closed / Lapsed

Wafer-level burn-in testing of integrated circuits

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