Method and integrated circuit adapted for partial scan testability

Claim 1

A method of testing a digital integrated circuit including combinational logic and a set of memory elements whose state is affected by the combinational logic, the method comprising the steps of: establishing a test mode of a circuit by isolating from the combinational logic a subset of the memory elements of the integrated circuit, said members of the subset being chosen such that, while in the test mode, substantially all feedback paths equal to or greater than a selected cycle length in the circuit are eliminated, wherein a feedback path is defined as a signal path from an output of a memory element to a functional data input of the memory element and the cycle length of a feedback path is defined as the number of other memory elements in the feedback path and loading test data into the isolated memory elements; placing the integrated circuit into an operational non-test mode for a predetermined test period; at the expiration of the test period, reestablishing the test mode of the circuit; and reading the state of the isolated memory elements.

Claim 2

A method of testing a digital integrated circuit including combinational logic and a set of memory elements whose state is affected by the combinational logic, the method comprising the steps of: establishing a test mode of a circuit by isolating from the combinational logic a subset of the memory elements of the integrated circuit, said members of the subset being chosen such that, while in the test mode, substantially all feedback paths equal to or greater than a selected cycle length in the circuit are eliminated, wherein a feedback path is defined as a signal path from an output of a memory element to a functional data input of the memory element and the cycle length of a feedback path is defined as the number of other memory elements in the feedback path and loading test data into the isolated memory elements; placing the integrated circuit into an operational non-test mode for a predetermined test period; at the expiration of the test period, reestablishing the test mode of the circuit; and reading the state of the isolated memory elements.

Claim 5

A method of designing a digital integrated circuit including combinational logic and a set of memory elements whose state is affected by the combinational logic for partial scan testing of the integrated circuit, characterized by the steps of: identifying those memory elements of a circuit that each contain a feedback path from an output of the memory element to a functional data input of the memory element, selecting from the identified memory elements a subset sufficient to eliminate substantially all said feedback paths in the circuit equal to or greater than a selected cycle length, wherein the cycle length of a feedback path is defined as the number of other memory elements in the feedback path, and adding circuitry to the circuit to control its operation in a functional mode and the scan test mode, in which in the functional mode the circuit, including the memory elements of the subset, operates in accordance with the intended function of the chip, and in the scan test mode, the functional data inputs of substantially all of the subset of memory elements are isolated from the combinational logic and made available for the acceptance of test data.

Claim 6

A method of designing a digital integrated circuit including combinational logic and a set of memory elements whose state is affected by the combinational logic for partial scan testing of the integrated circuit, characterized by the steps of: identifying those memory elements of a circuit that each contain a feedback path from an output of the memory element to a functional data input of the memory element, selecting from the identified memory elements a subset sufficient to eliminate substantially all said feedback paths in the circuit equal to or greater than a selected cycle length, wherein the cycle length of a feedback path is defined as the number of other memory elements in the feedback path, and adding circuitry to the circuit to control its operation in a functional mode and the scan test mode, in which in the functional mode the circuit, including the memory elements of the subset, operates in accordance with the intended function of the chip, and in the scan test mode, the functional data inputs of substantially all of the subset of memory elements are isolated from the combinational logic and made available for the acceptance of test data.