US4942577A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit system with latch circuits for reliable scan-path testing
Assignee: NEC Corp
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Filing: 1988-04-21
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Granted: 1990-07-17
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Expires: 2008-04-21
Abstract
Abstract An IC logic circuit includes a combinational network of a plurality of logic circuits, a plurality of latches having a D-type flip-flop and a delay circuit, the output from the D-type flip-flop being directly applied to one of the logic circuits and indirectly derived through the delay circuit, a plurality of selectors disposed between two latches to selectively applying an output from the logic circuit or an output from the preceding stage latch to the succeeding stage latch, and a means for supplying clock signal to said D-type flip-flops, a delay time of the delay circuit being longer than a time period spending in the clock signal supplying means.
Inventors
- 👤 Hideharu Ozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318552; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
278 words
A logic circuit system comprising: a plurality of logic circuits; a plurality of latch circuits each having an input terminal, a first output terminal, a second output terminal and a clock terminal and including a flip-flop and a delay circuit, said flip-flop having a data input node connected to said input terminal, a data output node connected to said first output terminal and a clock input node connected to said clock terminal, said delay circuit having an input node connected between said data output node of said flip-flop and said second output terminal, said first output terminal being further connected to one of said logic circuits to apply a signal at said first output terminal to said one logic circuit; a plurality of selectors having a first selector input terminal connected to said second output terminal, a second selector input terminal connected to a different one of said logic circuits to receive a signal from said different one logic circuit, a selector output terminal connected to said input terminal, and a control signal terminal; a control means for producing a control signal to be applied to said control signal terminal to selectively connect said selector output terminal to one of said first and second selector input terminals, said plurality of latch circuits being connected to form a shift-register when said selector output terminal is connected to said first selector input terminal and being connected to form a logic circuit with said plurality of logic circuits when said selector output terminal is connected to said second selector input terminal; and means for applying a clock signal to said clock input node to operate the flip-flops of said latch circuits.
Claim 2
Dependent Claim
278 words
A logic circuit system comprising: a plurality of logic circuits; a plurality of latch circuits each having an input terminal, a first output terminal, a second output terminal and a clock terminal and including a flip-flop and a delay circuit, said flip-flop having a data input node connected to said input terminal, a data output node connected to said first output terminal and a clock input node connected to said clock terminal, said delay circuit having an input node connected between said data output node of said flip-flop and said second output terminal, said first output terminal being further connected to one of said logic circuits to apply a signal at said first output terminal to said one logic circuit; a plurality of selectors having a first selector input terminal connected to said second output terminal, a second selector input terminal connected to a different one of said logic circuits to receive a signal from said different one logic circuit, a selector output terminal connected to said input terminal, and a control signal terminal; a control means for producing a control signal to be applied to said control signal terminal to selectively connect said selector output terminal to one of said first and second selector input terminals, said plurality of latch circuits being connected to form a shift-register when said selector output terminal is connected to said first selector input terminal and being connected to form a logic circuit with said plurality of logic circuits when said selector output terminal is connected to said second selector input terminal; and means for applying a clock signal to said clock input node to operate the flip-flops of said latch circuits.
Claim 3
Dependent Claim
15 words
A logic circuit system as claimed in claim 1, wherein said flip-flop is D-type flip-flop.
Claim 4
Dependent Claim
22 words
A logic circuit system as claimed in claim 2, wherein said delay circuit has a delay time of 5 to 25 nano-seconds.
Claim 5
Dependent Claim
48 words
A logic circuit system as claimed in claim 3, wherein said delay circuit has a cascade connection of two inverters and a capacitor having a capacitance of 5 to 10 pF, said capacitor being inserted between an interconnection path of said two inverters and a fixed potential point.
Claim 6
Dependent Claim
41 words
A logic circuit system as claimed in claim 1, further comprising a scan-in terminal receiving test data to be applied to said logic circuit through said shift-register, and a scan-out terminal deriving output signals of said logic circuit through said shift-register.
Claim 7
Dependent Claim
154 words
A shift-register comprising: a plurality of latches connected to form a cascade connection, each of said latches having a data input terminal, a clock terminal and a data output terminal and including a flip-flop having a data input node connected to said data input terminal to receive an input data from a preceding stage latch, a data output node and a clock input node, and a delay circuit having an input node connected to said data output node and an output node connected to said data output terminal which is connected to said data input terminal in a succeeding stage latch; an input terminal receiving said input data to apply it to said data input terminal of a first stage latch; an output terminal connected to said data output terminal in a final stage latch; and means for supplying a clock signal to the clock terminals of said latches to operate the flip-flops thereof.
Claim 8
Dependent Claim
154 words
A shift-register comprising: a plurality of latches connected to form a cascade connection, each of said latches having a data input terminal, a clock terminal and a data output terminal and including a flip-flop having a data input node connected to said data input terminal to receive an input data from a preceding stage latch, a data output node and a clock input node, and a delay circuit having an input node connected to said data output node and an output node connected to said data output terminal which is connected to said data input terminal in a succeeding stage latch; an input terminal receiving said input data to apply it to said data input terminal of a first stage latch; an output terminal connected to said data output terminal in a final stage latch; and means for supplying a clock signal to the clock terminals of said latches to operate the flip-flops thereof.
Claim 9
Dependent Claim
59 words
A shift-register as claimed in claim 6, wherein said delay circuit has a first delay time for transmitting a signal from said input node to said output node, said clock signal supplying means having a signal path having a second delay time for transmitting said clock signal therethrough, said first delay time being longer than said second delay time.
Claim 10
Dependent Claim
17 words
A shift-register as claimed in claim 7, wherein said first delay time is 5 to 25 nano-seconds.
Claim 11
Dependent Claim
48 words
A shift-register as claimed in claim 8, wherein said delay circuit has two inverters connected to form a cascade connection and a capacitor having a capacitance of 5 to 10 pF, said capacitor being connected between an interconnecting portion of said two inverters and a reference potential point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |