Self diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI

Claim 3

A method as defined in claim 1, wherein steps (a) through (f) are repeated for subsequent logic devices in the integrated circuit.

Claim 4

A method as defined in claim 2, and further comprising the step of controlling said isolating, presetting, clocking, and comparing steps.

Claim 5

A method as defined in claim 2, wherein said isolating step includes connecting a data switch with each input to a logic device on an integrated circuit under test and controlling the data switches to disconnect the input from the logic device under test during the testing operation.

Claim 6

A method as defined in claim 4, and further comprising the step of initiating the test sequence from a remote location.

Claim 7

A method as defined in claim 4, wherein said logic device has inputs from a buss structure which operates as an input/output device, and further comprising the step of doubling the testing cycle, whereby said buss structure is treated as an input circuit during the first testing cycle and as an output circuit during the second testing cycle.

Claim 8

A method as defined in claim 6, wherein steps (a) through (f) are performed internally to provide built-in-test of the integrated circuit device.

Claim 9

A method as defined in claim 1, wherein steps (b) through (f) are performed externally to the integrated circuit device by a separate testing device.

Claim 10

A method as defined in claim 1, and further comprising the step of presetting the memory elements to a plurality of known start settings each having known stop settings following normal fault-free operation.

Claim 11

Apparatus for testing an integrated circuit including a plurality of inputs, a plurality of outputs, and a plurality of logic devices connected between the inputs and outputs each of the logic devices including a plurality of logic gates and memory elements, comprising (a) means connected with each input for isolating a first logic device under test from external signals applied via the inputs of the remaining logic devices; (b) test controller means connected with each of said isolation means and with said first logic device for controlling the testing sequence of said logic device, said controller means including (1) means for reconfiguring said logic device to include all logic gates and memory elements to simulate a non-linear binary sequence generator; (2) means connected with said memory elements for presetting said memory elements to a known start setting; (3) means for clocking said logic device for a given number of steps to define a testing cycle to operate the logic gates and memory elements as a non-linear binary sequence generator, the memory elements achieving known settings under normal operating conditions and different settings under fault conditions; (4) means connected with said memory elements for sensing the settings of the memory elements after the testing cycle and for comparing the settings with the known setting; and (c) indicator means connected with said comparing means for indicating a fault condition when the settings of the memory elements are different from the known setting.

Claim 12

Apparatus for testing an integrated circuit including a plurality of inputs, a plurality of outputs, and a plurality of logic devices connected between the inputs and outputs each of the logic devices including a plurality of logic gates and memory elements, comprising (a) means connected with each input for isolating a first logic device under test from external signals applied via the inputs of the remaining logic devices; (b) test controller means connected with each of said isolation means and with said first logic device for controlling the testing sequence of said logic device, said controller means including (1) means for reconfiguring said logic device to include all logic gates and memory elements to simulate a non-linear binary sequence generator; (2) means connected with said memory elements for presetting said memory elements to a known start setting; (3) means for clocking said logic device for a given number of steps to define a testing cycle to operate the logic gates and memory elements as a non-linear binary sequence generator, the memory elements achieving known settings under normal operating conditions and different settings under fault conditions; (4) means connected with said memory elements for sensing the settings of the memory elements after the testing cycle and for comparing the settings with the known setting; and (c) indicator means connected with said comparing means for indicating a fault condition when the settings of the memory elements are different from the known setting.

Claim 13

Apparatus as defined in claim 10, wherein said isolation means comprises a plurality of data switch elements connected with the inputs, respectively.

Claim 14

Apparatus as defined in claim 11, and further comprising a plurality of feedback circuits connecting the outputs of said logic device with the inputs to said data switch elements, respectively, whereby said logic device is reconfigured to include all logic gates and memory elements to simulate a non-linear sequence generator and further whereby said memory elements detect and store any faults during the testing clock cycle.

Claim 15

Apparatus as defined in claim 12, wherein said comparing means comprises an AND gate.

Claim 16

Apparatus as defined in claim 13, and further comprising input/output buss means connected with the inputs, and further wherein the test cycle is doubled, whereby said buss means is treated as an input circuit during the first testing cycle and as an output circuit during the second testing cycle.

Claim 17

Apparatus as defined in claim 14, and further comprising means for actuating said controller means for initiating a testing cycle.