US5038191A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-03-01
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Granted: 1991-08-06
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Expires: 2010-03-01
Abstract
Abstract A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.
Inventors
- 👤 Takehiro Hasegawa
- 👤 Koji Sakui
- 👤 Shigeyoshi Watanabe
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/41; G11C11/411; G11C11/4113; G11C11/412
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
132 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; an array of memory cells each including a bipolar transistor and a switching element, each bipolar transistor having a base, a collector and an emitter in which a collector-emitter voltage is controlled by a voltage applied between the collector and the emitter so that a polarity of a base current is changed in accordance with an increase in a base-emitter voltage, and each switching element being provided between the base of a bipolar transistor and one of said bit lines and controllable through one of said word lines; and current changing means for changing a value of a current flowing through the collector of each of said bipolar transistor between a stationary state and an active state.
Claim 2
Dependent Claim
132 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; an array of memory cells each including a bipolar transistor and a switching element, each bipolar transistor having a base, a collector and an emitter in which a collector-emitter voltage is controlled by a voltage applied between the collector and the emitter so that a polarity of a base current is changed in accordance with an increase in a base-emitter voltage, and each switching element being provided between the base of a bipolar transistor and one of said bit lines and controllable through one of said word lines; and current changing means for changing a value of a current flowing through the collector of each of said bipolar transistor between a stationary state and an active state.
Claim 3
Dependent Claim
34 words
A semiconductor memory device according to claim 1, wherein said current changing means includes means for changing a potential of said collector of said bipolar transistor between said stationary state and said active state.
Claim 4
Dependent Claim
43 words
A semiconductor memory device according to claim 1, wherein said current changing means has a resistor element coupled to said emitter of said bipolar transistor and means for changing a resistance value of said resistor element between said stationary and said active state.
Claim 5
Dependent Claim
58 words
A semiconductor memory device according to claim 1, wherein said current changing means has a resistor element coupled to said emitter of said bipolar transistor and means for changing at least one of a potential of said collector of said bipolar transistor and a resistance value of said resistor element between said stationary state and said active state.
Claim 6
Dependent Claim
80 words
A semiconductor memory device according to claim 1, wherein said array of memory cells is divided into a plurality of cell block arrays in association with addresses, and said current changing means has a resistor element coupled to said emitter of said bipolar transistor and means for changing at least one of a potential of said collector and a resistance value of said resistor element for each of said cell block arrays between said stationary state and said active state.
Claim 7
Dependent Claim
87 words
A semiconductor memory device according to claim 1, wherein said array of memory cells is divided into a plurality of cell block arrays in association with addresses, and said current changing means has a resistor element coupled to said emitter of said bipolar transistor and means for changing at least one of a potential of said collector and a resistance value of said resistor element for each of said cell block arrays which is arranged along each word line, between said stationary state and said active state.
Claim 8
Dependent Claim
53 words
A semiconductor memory device according to claim 1, wherein said current changing means comprises means for selectively applying a voltage of a first level and a voltage of a second level higher than said first level to said collector of said bipolar transistor in accordance with said stationary state and said active state.
Claim 9
Dependent Claim
36 words
A semiconductor memory device according to claim 7, wherein said voltage applying means comprises switching means, coupled to said collector of said bipolar transistor, for switching between said first level voltage and said second level voltage.
Claim 10
Dependent Claim
76 words
A semiconductor memory device according to claim 1, wherein said current changing means comprises a plurality of voltage applying means, provided in association with said word lines, for selectively applying a voltage of a first level and a voltage of a second level higher than said first level to said collectors of said bipolar transistors of said array of memory cells associated with said word lines, in accordance with said stationary state and said active state.
Claim 11
Dependent Claim
82 words
A semiconductor memory device according to claim 1, wherein said array of memory cells is divided into a plurality of memory array groups, and said current changing means comprises means, coupled to each of said memory array groups, for selectively applying a voltage of a first level and a voltage of a second level higher than said first level to said collectors of said bipolar transistors in an associated memory array group in accordance with said stationary state and said active state.
Claim 12
Dependent Claim
72 words
A semiconductor memory device according to claim 1, wherein said current changing means comprises a plurality of variable resistor elements, provided for said word lines, respectively and each coupled to said emitters of said bipolar transistors in those of said array of memory cells which are associated with each of word lines, for changing a current to be supplied to said emitters in accordance with said stationary state and said active state.
Claim 13
Dependent Claim
20 words
A semiconductor memory device according to claim 11, wherein said variable resistor elements are each constituted by an nMOS transistor.
Claim 14
Dependent Claim
76 words
A semiconductor memory device according to claim 1, wherein said array of memory cells is divided into a plurality of memory array groups, and said current changing means comprises means, coupled to each of said memory array groups, for selectively applying a first current and a second current higher than said first current to said emitters of said bipolar transistors in an associated memory array group in accordance with said stationary state and said active state.
Claim 15
Dependent Claim
160 words
A semiconductor memory device comprising: a memory array section including a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in said column and to be supplied with a control clock; and a plurality of bit lines arranged in said row and to be supplied with an input signal; each of said memory cells including a bipolar transistor and a switching element, each bipolar transistor having a base, a collector and an emitter in which a collector-emitter voltage is controlled by a voltage applied between the collector and the emitter so that a polarity of a base current is changed in accordance with an increase in a base-emitter voltage, and each switching element being controllable by one of said word lines; said memory arrange section having current changing means for changing a level of a current flowing through the collector of each of said bipolar transistors between an active state and a stationary state.
Claim 16
Dependent Claim
160 words
A semiconductor memory device comprising: a memory array section including a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in said column and to be supplied with a control clock; and a plurality of bit lines arranged in said row and to be supplied with an input signal; each of said memory cells including a bipolar transistor and a switching element, each bipolar transistor having a base, a collector and an emitter in which a collector-emitter voltage is controlled by a voltage applied between the collector and the emitter so that a polarity of a base current is changed in accordance with an increase in a base-emitter voltage, and each switching element being controllable by one of said word lines; said memory arrange section having current changing means for changing a level of a current flowing through the collector of each of said bipolar transistors between an active state and a stationary state.
Claim 17
Dependent Claim
37 words
A semiconductor memory device according to claim 14, wherein said current changing means comprises means for applying a lower collector voltage to said collector of said bipolar transistor in said active state than in said stationary state.
Claim 18
Dependent Claim
37 words
A semiconductor memory device according to claim 14, wherein said current changing means comprises means for supplying a lower emitter current to said emitter of said bipolar transistor in said active state than in said stationary state.
Claim 19
Dependent Claim
39 words
A semiconductor memory device according to claim 16, wherein said emitter current supplying means has a variable resistor element coupled to said emitter and having a resistance value variable in accordance with said stationary state and said active state.
Claim 20
Dependent Claim
56 words
A semiconductor memory device according to claim 14, wherein said current changing means has a resistor element coupled to said emitter of said bipolar transistor and means for changing at least one of a collector potential of said bipolar transistor and a resistance value of said resistor element between said stationary state and said active state.
Claim 21
Dependent Claim
58 words
A semiconductor memory device according to claim 14, wherein said memory cell array section is divided into a plurality of cell array groups in association with addresses and said current changing means has means for changing at least one of an emitter current flowing through said emitter and a collector potential for each of said cell array groups.
Claim 22
Dependent Claim
72 words
A semiconductor memory device according to claim 14, wherein said memory cell array section is divided into a plurality of cell array groups in association with addresses, and said current changing means has a resistor element coupled to said emitter and means for changing at least one of a collector potential and a resistance value of said resistor element for each of said memory cell array groups arranged along each word line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-05 | 1995-02-04 | 1995-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-05 | 1999-02-04 | 1999-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-05 | 2003-02-04 | 2003-08-06 | $7700.00 | Window Closed / Lapsed |