Circuit arrangement for removing carriers in a transistor

Claim 2

A circuit arrangement for switching a current through the emitter-collector path of a bipolar transistor having a base connection comprising: means for applying a substantially square-wave signal to said base connection from a switching signal generator via a series connected two-terminal network including an inductive reactance, said signal alternately switching the transistor to a conducting saturation state and to a non-conducting state, characterized in that the two-terminal network is of such a structure that the value of the inductive reactance decreases responsive to an increase of a current flowing through the two-terminal network.

Claim 3

A circuit arrangement as claimed in claim 1, characterized in that the two-terminal network comprises a coil having a core of magnetizable material which is magnetized into the saturated state by a negative current flowing in the base connection of the transistor when said square-wave signal switches the transistor from the conducting saturation state to the non-conducting state, and wherein said coil is magnetically isolated from the collector of the transistor.

Claim 4

A high speed transistor switching circuit for switching a transistor between a saturation condition and a cut-off condition comprising: a source of square wave switching signal coupled to a base electrode of said transistor via a two-terminal network that includes an inductive reactance operative to accelerate the removal of minority charge carriers from the base-collector region of the transistor when the switching signal drives the transistor from the saturation condition to the cut-off condition, said two-terminal network being connected in series between an output terminal of said switching signal source and the transistor base electrode so that a negative base current flows through said inductive reactance, the two-terminal network producing a decrease in the inductive reactance when said negative base current flowing through the two-terminal network increases above a given level.

Claim 5

A high speed transistor switching circuit for switching a transistor between a saturation condition and a cut-off condition comprising: a source of square wave switching signal coupled to a base electrode of said transistor via a two-terminal network that includes an inductive reactance operative to accelerate the removal of minority charge carriers from the base-collector region of the transistor when the switching signal drives the transistor from the saturation condition to the cut-off condition, said two-terminal network being connected in series between an output terminal of said switching signal source and the transistor base electrode so that a negative base current flows through said inductive reactance, the two-terminal network producing a decrease in the inductive reactance when said negative base current flowing through the two-terminal network increases above a given level.

Claim 6

A high speed switching circuit as claimed in claim 3 wherein said inductive reactance produces a non-linear current characteristic for the negative base current flowing through the two-terminal network during the transition of the transistor from the saturation condition to the cut-off condition.

Claim 7

A high speed switching circuit as claimed in claim 3 wherein said inductive reactance of the two-terminal network comprises a saturable reactor having a coil through which the negative base current flows during the transition of the transistor from the saturation condition to cut-off condition, said negative base current driving the saturable reactor into saturation with a time delay approximately equal to the storage time of the transistor.

Claim 8

A high speed switching circuit as claimed in claim 3 wherein said inductive reactance of the two-terminal network produces a hysteresis type current characteristic for negative base current flowing in the two-terminal network during the transition of the transistor from the saturation condition to the cut-off condition.

Claim 9

A high speed switching circuit as claimed in claim 6 wherein the inductive reactance of the two-terminal network comprises a saturable reactor having a coil through which the negative base current flows and drives the saturable reactor into saturation during the transition of the transistor from the saturation condition to the cut-off condition.

Claim 10

A circuit arrangement as claimed in claim 1 wherein said inductive reactance is connected in the two-terminal network so that the inductive reactance passes base current in both a positive and negative direction, said negative base current flowing when the switching signal drives the transistor from the conducting state to the non-conducting state, said inductive reactance decreasing to a low value during the period when the negative base current flows and due solely to said negative base current.

Claim 11

A circuit arrangement as claimed in claim 1 wherein said two-terminal network comprises a bidirectional network that provides approximately the same impedance to current flow in either direction thereof.

Claim 12

A circuit arrangement as claimed in claim 1 wherein said inductive reactance comprises a saturable reactor which passes a negative base current when the switching signal drives the transistor into the non-conducting state, said saturable reactor then being operative in responsive to the negative base current flowing therein to remove minority charge carriers from the base-collector region of the transistor.

Claim 13

A high-speed switching circuit as claimed in claim 3 wherein said inductive reactance of the two-terminal network comprises a saturable reactor through which the negative base current flows during the transition of the transistor from the saturation condition to the cut-off condition, said saturable reactor passing a positive base current when the transistor is in the saturation condition.