Microcomputer with high density ram in separate isolation well on single chip

Claim 2

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation region in said substrate, said first isolation region being of the same type of material as that of said substrate and containing all of said memory cells of said high density RAM array, and (f) a second isolation region separate from said first isolation region and being of the same type of material as that of said substrate, said second isolation region containing some of said transistors which are operable independently of said operation of said RAM, (g) isolation means formed in said substrate for isolating said first and second regions, whereby said high density RAM is located on the same chip as said independently operation transistors and is protected from noise due to independent operation of said transistors.

Claim 3

A microcomputer according to claim 1 wherein said isolation means is a well.

Claim 4

A microcomputer according to claim 1 wherein said isolation means is a well having a conductivity opposite to that of said substrate.

Claim 5

A microcomputer according to claim 1 wherein said first isolation region comprises a plurality of isolation regions each containing a portion of said memory cells of said RAM array.

Claim 6

A microcomputer according to claim 1 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 7

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operably independently of the operation of said RAM, (e) a first isolation well formed in said substrate of a semiconductor material of different type of material than said substrate and defining a first isolation region in said substrate, said first isolation region being of the same type of material as said substrate, (f) a second isolation well formed in said substrate of a semiconductor material of different type than said substrate, said first isolation region or said second well containing all of said memory cells of said high density RAM array, the other containing some of said transistors which are operable independently of said operation of said RAM, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 8

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operably independently of the operation of said RAM, (e) a first isolation well formed in said substrate of a semiconductor material of different type of material than said substrate and defining a first isolation region in said substrate, said first isolation region being of the same type of material as said substrate, (f) a second isolation well formed in said substrate of a semiconductor material of different type than said substrate, said first isolation region or said second well containing all of said memory cells of said high density RAM array, the other containing some of said transistors which are operable independently of said operation of said RAM, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 9

A microcomputer according to claim 6 wherein said isolation well surrounds said first isolation region.

Claim 10

A microcomputer according to claim 6 wherein the first of said isolation regions comprises a plurality of isolation regions each containing a portion of said memory cells of said high density RAM array.

Claim 11

A microcomputer according to claim 6 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 12

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for reeving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation region in said substrate, said first isolation region containing all of said memory cells of said high density RAM array, and (f) a second isolation region in said substrate separate from said firs isolation region, said second isolation region containing some of said transistors which are operable independently of said operation of said RAM, said firs and second regions noise isolated from each other, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 13

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for reeving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation region in said substrate, said first isolation region containing all of said memory cells of said high density RAM array, and (f) a second isolation region in said substrate separate from said firs isolation region, said second isolation region containing some of said transistors which are operable independently of said operation of said RAM, said firs and second regions noise isolated from each other, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 14

A microcomputer according to claim 10 wherein said first isolation region comprises a plurality of isolation regions each containing a portion of said memory cells of said RAM array.

Claim 15

A microcomputer according to claim 10 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 16

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on chip memory comprises a high density RAM array having at lest 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of the same type of semiconductor material as said substrate, (f) a second isolation well or wells formed in said substrate separate from said first isolation well or wells and formed of a semiconductor material of different type than said substrate, all of said memory cells of said high density RAM array being contained in either said first or said second isolation well or wells, some of said transistors which are operable independently of the operation of said RAM being contained in the other of said first or second isolation well or wells, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 17

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on chip memory comprises a high density RAM array having at lest 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of the same type of semiconductor material as said substrate, (f) a second isolation well or wells formed in said substrate separate from said first isolation well or wells and formed of a semiconductor material of different type than said substrate, all of said memory cells of said high density RAM array being contained in either said first or said second isolation well or wells, some of said transistors which are operable independently of the operation of said RAM being contained in the other of said first or second isolation well or wells, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 18

A microcomputer according to claim 13 including a third isolation well formed around said first isolation well or wells, said third isolation well being of a different type of material than that of said substrate.

Claim 19

A microcomputer according to claim 13 wherein said first isolation well comprises a plurality of isolation wells each containing a portion of said memory cells of said RAM array.

Claim 20

A microcomputer according to claim 13 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 21

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of a semiconductor material having the same conductivity type but different resistivity than said substrate, (f) a second isolation well or wells formed in said substrate separate from said first isolation well or wells and formed of a semiconductor material having the same conductivity type but different resistivity than said substrate, either of said first or said second isolation well or wells containing all of said memory cells of said high density RAM array, the other of said first or said second isolation well or wells containing some of said transistors which are operable independently of said operation of said RAM, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 22

A microcomputer comprising an on-chip processor and an on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of a semiconductor material having the same conductivity type but different resistivity than said substrate, (f) a second isolation well or wells formed in said substrate separate from said first isolation well or wells and formed of a semiconductor material having the same conductivity type but different resistivity than said substrate, either of said first or said second isolation well or wells containing all of said memory cells of said high density RAM array, the other of said first or said second isolation well or wells containing some of said transistors which are operable independently of said operation of said RAM, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 23

A microcomputer according to claim 17 wherein the one of said first or said second isolation wells comprises a plurality of wells each containing a portion of said memory cells of said RAM array.

Claim 24

A microcomputer according to claim 17 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 25

A microcomputer comprising an on-chip processor and on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of a semiconductor material of a different type than said substrate, (f) a first region formed in said substrate, said first region defined by said first isolation well or wells, said first region being of the same type of semiconductor material as said substrate of said memory cells, all of said high density RAM array being contained in either said first isolation well or wells or in said first region, some of said transistors which are operable independently of said operation of said RAM being contained in the other of said first isolation well or wells or in said first region, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 26

A microcomputer comprising an on-chip processor and on-chip memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip memory comprises a high density RAM array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said RAM to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said RAM for receiving said instructions from said program stored in said RAM, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said RAM, (e) a first isolation well or wells formed in said substrate of a semiconductor material of a different type than said substrate, (f) a first region formed in said substrate, said first region defined by said first isolation well or wells, said first region being of the same type of semiconductor material as said substrate of said memory cells, all of said high density RAM array being contained in either said first isolation well or wells or in said first region, some of said transistors which are operable independently of said operation of said RAM being contained in the other of said first isolation well or wells or in said first region, whereby said high density RAM is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 27

A microcomputer according to claim 20 wherein the one of said first well or wells and said first region comprises a plurality of wells or regions each containing a portion of said memory cells of said RAM array.

Claim 28

A microcomputer according to claim 20 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.

Claim 29

A microcomputer comprising an on-chip processor and an on-chip writable memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip writable memory comprises a high density memory array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said memory array to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said memory array for receiving said instructions from said program stored in said memory array, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said memory array, (e) a first isolation region in said substrate, said first isolation region containing all of said memory cells of said high density memory array, and (f) a second isolation region in said substrate separate from said first isolation region, said second isolation region containing some of said transistors which are operable independently of said operation of said memory array, said first and second regions noise isolated from each other, whereby said high density memory array is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 30

A microcomputer comprising an on-chip processor and an on-chip writable memory on a single integrated circuit chip having a substrate of semiconductor material of a first type, wherein said on-chip writable memory comprises a high density memory array having at least 1K bytes for holding a sequence of instructions for execution by said on-chip processor, said microcomputer including: (a) an instruction pointer circuit for addressing said memory array to obtain program instructions therefrom, (b) an instruction receiving circuit coupled to said memory array for receiving said instructions from said program stored in said memory array, (c) an instruction decoder circuit coupled to said instruction receiving circuit for decoding instructions received by said instruction receiving circuit, (d) a plurality of on-chip transistors comprising circuitry operable independently of the operation of said memory array, (e) a first isolation region in said substrate, said first isolation region containing all of said memory cells of said high density memory array, and (f) a second isolation region in said substrate separate from said first isolation region, said second isolation region containing some of said transistors which are operable independently of said operation of said memory array, said first and second regions noise isolated from each other, whereby said high density memory array is located on the same chip as said independently operating transistors and is protected from noise due to independent operation of said transistors.

Claim 31

A microcomputer according to claim 23 wherein said first isolation region comprises a plurality of isolation regions each containing a portion of said memory cells of said memory array.

Claim 32

A microcomputer according to claim 23 wherein said substrate includes an epitaxial layer and said memory cells are located in said epitaxial layer.