US4587542A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Guard ring for reducing pattern sensitivity in MOS/LSI dynamic RAM
Assignee: Texas Instruments Inc
•
Filing: 1979-10-11
•
Granted: 1986-05-06
•
Expires: 1999-10-11
Abstract
Abstract An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:54
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
85 words
A semiconductor memory device comprising an array of memory cells in a face of a semiconductor body, peripheral circuitry in said face spaced from the array, and a guard region positioned in said face between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the guard region comprising a shallow heavily-doped region of opposite type over a much deeper heavily-doped region of one type, the body being of said one type but of much lighter doping level.
Claim 2
Dependent Claim
85 words
A semiconductor memory device comprising an array of memory cells in a face of a semiconductor body, peripheral circuitry in said face spaced from the array, and a guard region positioned in said face between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the guard region comprising a shallow heavily-doped region of opposite type over a much deeper heavily-doped region of one type, the body being of said one type but of much lighter doping level.
Claim 3
Dependent Claim
20 words
A device according to claim 1 wherein the body is P- conductivity and the memory cells include N-channel MOS transistors.
Claim 4
Dependent Claim
17 words
A device according to claim 1 wherein the guard region is a ring completely surrounding said array.
Claim 5
Dependent Claim
30 words
A device according to claim 1 wherein said heavily-doped region of said one type is at least about ten times deeper than said heavily doped region of said opposite type.
Claim 6
Dependent Claim
98 words
A semiconductor device comprising an array of cells sensitive to minority carrier drift, the cells being formed in a face of a semiconductor body, peripheral circuitry in said face spaced from the array, the peripheral circuitry generating minority carriers, and a guard region positioned in said face between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the guard region comprising a shallow very heavily-doped region of one type, over a heavily-doped region of the opposite type, the body being of said opposite type but of much lighter doping level.
Claim 7
Dependent Claim
98 words
A semiconductor device comprising an array of cells sensitive to minority carrier drift, the cells being formed in a face of a semiconductor body, peripheral circuitry in said face spaced from the array, the peripheral circuitry generating minority carriers, and a guard region positioned in said face between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the guard region comprising a shallow very heavily-doped region of one type, over a heavily-doped region of the opposite type, the body being of said opposite type but of much lighter doping level.
Claim 8
Dependent Claim
19 words
A device according to claim 5 wherein the body is P- conductivity and the cells include N-channel MOS transistors.
Claim 9
Dependent Claim
17 words
A device according to claim 5 wherein the guard region is a ring completely surrounding said array.
References Cited (Backward Citations)
US4044373A
Cited
US3573509A
Cited
US3863065A
Cited
DE2751592A1
Cited
DE2832764A1
Cited
US4160985A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |