Abstract A sigma-delta converter including a switching component controlled by a first clock having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes circuits for generating a second clock of a same frequency as the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the switching element occur during said defined period of time. There is also included a circuit controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses insensitive to the mismatch of the rise and fall times of the switching element thereby improving the linearity and the signal-to-noise ratio of the converter. The control of the period of time allows varying of the energy of the pulses in order to provide pulse trains which, when applied to a sigma-delta decoder, provide an analog output value representative of, but attenuated with respect to, the analog input value.
A sigma-delta converter including a switching component (313) controlled by determined transitions of a first clock signal (308) for generating a train of sigma-delta code pulses corresponding to an analog input value characterized in that said converter comprises: means (306, 310, 311) for generating a second clock signal of the same frequency as said first clock signal and having a first transition of a first polarity followed after a defined period of time (d2) by a second transition of a second polarity opposite to said first polarity transition, said determined transitions of said first clock signal occurring during said defined period of time; and means (305) controlled by said sigma-delta code pulse train and said second clock signal for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving a signal-to-noise ratio and linearity of the sigma-delta converter; and said converter further including means for varying said period of time in order to vary an energy of an elementary positive pulse of said sigma-delta pulse train in order to provide an attenuation function.
Claim 2
Dependent Claim
187 words
A sigma-delta converter including a switching component (313) controlled by determined transitions of a first clock signal (308) for generating a train of sigma-delta code pulses corresponding to an analog input value characterized in that said converter comprises: means (306, 310, 311) for generating a second clock signal of the same frequency as said first clock signal and having a first transition of a first polarity followed after a defined period of time (d2) by a second transition of a second polarity opposite to said first polarity transition, said determined transitions of said first clock signal occurring during said defined period of time; and means (305) controlled by said sigma-delta code pulse train and said second clock signal for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving a signal-to-noise ratio and linearity of the sigma-delta converter; and said converter further including means for varying said period of time in order to vary an energy of an elementary positive pulse of said sigma-delta pulse train in order to provide an attenuation function.
Claim 3
Dependent Claim
124 words
A sigma-delta converter according to claim 1 characterized in that said converter further includes: a third clock signal (301) having a frequency being equal to n times the frequency of said first clock signal means (315, 312) for dividing said third clock signal in order to provide said first clock signal means (302, 303) controlled by said third clock signal (301) for generating signals having different determined duty cycles corresponding to different attenuation values and having the same frequency than said first clock signal means (304) for choosing one among said signals of different duty cycles whereby providing a sigma-delta pulses which, when applied to a sigma-delta decoder, provides an analog output value being representative but attenuated with respect to said input analog value.