Delta modulated digital signal detector

Claim 2

A detector for delta modulated digital signals transmitted in a serial bit stream at a predetermined bit frequency of a clock signal, comprising: means for generating a clock signal; first counting means responsive to the clock signal for providing a reset pulse signal at the end of each successive N bit interval, where N is an integer; transition detection means responsive to the digital signal and the clock signal for providing a transition pulse signal for each change in logical state between successive bits of the digital signal; second counting means responsive to the transition pulse signals and reset pulse signals for repetitively providing totallized counts of the transition pulses occurring between successive reset pulse signals; means for storing at least the last two successive totallized counts; and means for providing a detect indication signal that the ditital signal is present when both of the stored totallized counts have a magnitude outside of a predetermined range of magnitudes centered about one-half of N.

Claim 3

The digital signal detector according to claim 1, further including means for integrating the detect indication signal to provide a quality signal having a magnitude proportional to the bit error rate of the digital signal.

Claim 4

The digital signal detector according to claim 2, for use in each of a plurality of receivers of a receiver voting system, wherein the receiver voting system includes comparator means responsive to the quality signals from the respective digital signal detectors in the receivers for selecting the receiver that is receiving the digital signal with the lowest bit error rate.

Claim 5

The digital signal detector according to claim 1, wherein the storing means includes means for storing the last M successive totallized counts, where M is an integer, and wherein the indication providing means provides a detect indication signal that the digital signal is present when a majority of the M stored totallized counts have magnitudes outside of the predetermined range of magnitudes.

Claim 6

The digital signal detector according to claim 1, wherein N is 16 and the predetermined range of magnitudes includes 8 and 9.

Claim 7

An error-burst detector for delta modulated digital signals transmitted in a serial bit stream at a predetermined bit frequency of a clock signal, the digital signals scrambled according to a predetermined coding scheme prior to transmission and unscrambled prior to application to the error-burst detector, a single bit error introduced during transmission of the digital signal causing a pseudorandom error burst when unscrambled, said error-burst detector comprising: means for generating a clock signal; first counting means responsive to the clock signal for providing a reset pulse signal at the end of successive N-bit intervals, where N is an integer; transition detection means responsive to the digital signal and the clock signal for providing a transition pulse signal for each change in logical state between successive bits of the digital signal; second counting means responsive to the transition pulse signals and reset pulse signals for repetitively providing totallized counts of the transition pulses occurring between successive reset pulse signals; means for storing at least the last two successive totallized counts; and means for providing an error-burst indication signal that an error burst is present when both of the stored totallized counts have a magnitude within a predetermined range of magnitudes centered about one-half of N.

Claim 8

An error-burst detector for delta modulated digital signals transmitted in a serial bit stream at a predetermined bit frequency of a clock signal, the digital signals scrambled according to a predetermined coding scheme prior to transmission and unscrambled prior to application to the error-burst detector, a single bit error introduced during transmission of the digital signal causing a pseudorandom error burst when unscrambled, said error-burst detector comprising: means for generating a clock signal; first counting means responsive to the clock signal for providing a reset pulse signal at the end of successive N-bit intervals, where N is an integer; transition detection means responsive to the digital signal and the clock signal for providing a transition pulse signal for each change in logical state between successive bits of the digital signal; second counting means responsive to the transition pulse signals and reset pulse signals for repetitively providing totallized counts of the transition pulses occurring between successive reset pulse signals; means for storing at least the last two successive totallized counts; and means for providing an error-burst indication signal that an error burst is present when both of the stored totallized counts have a magnitude within a predetermined range of magnitudes centered about one-half of N.

Claim 9

The error-burst detector according to claim 6, further including means for integrating the error-burst indication signal to provide a quality signal having a magnitude proportional to the bit error rate of the digital signal.

Claim 10

The error-burst detector according to claim 7, for use in each of a plurality of receivers of a receiver voting system, wherein the receiver voting system includes comparator means responsive to the quality signals from the respective digital signal detectors in the receivers for selecting the receiver that is receiving the digital signal with the lowest bit error rate.

Claim 11

The digital signal detector according to claim 6, wherein N is 16 and the predetermined range of magnitudes includes 8 and 9.

Claim 12

A detector for delta modulated digital signals transmitted in a serial bit stream at a predetermined bit frequency of a clock signal, comprising: means for generating a clock signal; a first N state counter responsive to the clock signal for providing a reset pulse signal at the end of successive N-bit intervals, where N is an integer; a first shift register having at least first and second stages responsive to the clock signal for serially receiving and storing at least two successive bits of the digital signal; exclusive OR gating circuitry coupled to the first and second stages of the first shift register for providing a transition pulse signal when bits stored in the first and second stages of the first shift register have different logical states; a second counter responsive to the transition pulse signals and reset pulse signals for repetitively providing totallized counts of the transition pulse signals occurring between successive reset pulse signals; first gating circuitry responsive to the totallized counts from the second counter for providing an output signal having a predetermined first logical state when the totallized count has a magnitude within a predetermined range of magnitudes centered about one-half of N, and a predetermined second logical state when the totallized count is outside of the predetermined range of magnitudes; a second shift register having at least two stages responsive to the reset pulse signals for serially receiving and storing at least the last two successive output signals from the first gating circuitry; and second gating circuitry for combining the stored output signals from the second shift register to provide a detect indication signal that the digital signal is present when both of the stored output signals have a predetermined second logical state.

Claim 13

A detector for delta modulated digital signals transmitted in a serial bit stream at a predetermined bit frequency of a clock signal, comprising: means for generating a clock signal; a first N state counter responsive to the clock signal for providing a reset pulse signal at the end of successive N-bit intervals, where N is an integer; a first shift register having at least first and second stages responsive to the clock signal for serially receiving and storing at least two successive bits of the digital signal; exclusive OR gating circuitry coupled to the first and second stages of the first shift register for providing a transition pulse signal when bits stored in the first and second stages of the first shift register have different logical states; a second counter responsive to the transition pulse signals and reset pulse signals for repetitively providing totallized counts of the transition pulse signals occurring between successive reset pulse signals; first gating circuitry responsive to the totallized counts from the second counter for providing an output signal having a predetermined first logical state when the totallized count has a magnitude within a predetermined range of magnitudes centered about one-half of N, and a predetermined second logical state when the totallized count is outside of the predetermined range of magnitudes; a second shift register having at least two stages responsive to the reset pulse signals for serially receiving and storing at least the last two successive output signals from the first gating circuitry; and second gating circuitry for combining the stored output signals from the second shift register to provide a detect indication signal that the digital signal is present when both of the stored output signals have a predetermined second logical state.

Claim 14

The digital signal detector according to claim 10, wherein the delta modulated digital signal is scrambled according to a predetermined code prior to transmission and unscrambled prior to application to the digital signal detector, single bit errors occurring during transmission causing in the unscrambled digital signal an error burst having a pseudorandom data pattern lasting essentially over 2 N bits.

Claim 15

The digital signal detector according to claim 11, further including means for integrating the detect indication signal to provide a quality signal having a magnitude proportional to the bit error rate of the digital signal.

Claim 16

The digital signal detector according to claim 12, wherein the predetermined coding scheme includes a predetermined binary convolution code.

Claim 17

The digital signal detector according to claim 13, for use in each of a plurality of receivers of a receiver voting system, wherein the receiver voting system includes comparator means responsive to the quality signals from the respective digital signal detectors in the receivers for selecting the receiver that is receiving the digital signal with the lowest bit error rate.

Claim 18

The digital signal detector according to claim 14, wherein N is 16 and the predetermined range of magnitudes includes 8 and 9.

Claim 19

The digital signal detector according to claim 10 or 12, further including a semiconductive substrate, said digital signal detector comprised of electrical circuit elements integrated into the semiconductive substrate.