Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions

Claim 1

An improved process for the fabrication of CMOS integrated circuits on semiconductor material having both N-type material regions and P-type material regions, each of which is covered by a gate dielectric layer, said process comprising the following sequence of steps: a) a blanket deposition of conductive layer on top of the gate dielectric layer; b) masking of said conductive layer with a first photomask which, in P-type material regions, defines N-channel gates and interconnects, and in N-type material regions, blankets said conductive layer; c) etching away unmasked portions of said conductive layer and underlying portions of the gate dielectric layer to form N-channel gates and interconnects; d) stripping said first photomask; e) implantation of a P-type conductivity-creating impurity self-aligned to said N-channel gates which functions as a punchthrough implant, the conductive layer masking the N-type regions from the implanted P-type impurity; f) creation of a mini-spacer oxide layer on at least N-channel transistor gate sidewalls; g) low-dosage implantation of an N-type conductivity-creating impurity to create lightly-doped drain and source regions self-aligned to said mini-spacer oxide layer, the conductive layer masking the N-type material regions from this low-dosage implantation of an N-type impurity; h) blanket deposition of a first silicon dioxide layer; i) anisotropic etching of said first silicon dioxide layer to create N-channel transistor gate sidewall spacers; j) high-dosage implantation of an N-type conductivity-creating impurity to create heavily-doped drain and source regions self-aligned to said N-channel transistor gate sidewall spacers, the conductive layer masking the N-type material regions from this high-dosage implantation of an N-type impurity; k) using a second photomask to blanket the P-type material regions and to define P-channel gates and interconnects in the N-type material regions; l) etching away unmasked portions of said conductive layer and underlying portions of the gate dielectric layer to form P-channel gates and interconnects; m) low-dosage implantation of a P-type conductivity-creating impurity to create lightly-doped drain and source regions self-aligned to said P-channel gates, said second photomask blocking this low-dosage implantation of a P-type impurity in the P-type material regions; n) blanket deposition of a second silicon dioxide layer; o) anisotropic etching of said second silicon oxide layer to create P-channel transistor gate sidewall spacers; p) unmasked high-dosage implantation of a P-type conductivity-creating impurity to create heavily-doped drain and source regions self-aligned to said P-channel transistor gate sidewall spacers, said unmasked high dosage implantation being effected at a level that is substantially less than that employed for said high-dosage implantation of an N-type conductivity-creating impurity which created the heavily-doped drain and source regions; and q) silicidation of all exposed silicon regions.