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US5019889A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Hitachi Ltd
•
Filing: 1990-02-08
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Granted: 1991-05-28
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Expires: 2010-02-08
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Abstract

Abstract In an oscillation circuit consisting of an amplification circuit portion composed of transistors of input/output circuit basic cells of a gate array disposed on a semiconductor pellet and an oscillator disposed outside the semiconductor pellet, the amplification circuit portion consists of transistors for an output circuit of the input/output buffer circuit basic cells. The dielectric breakdown characteristics of the amplification circuit portion of the oscillation circuit can be improved because the structure of the transistor for the output circuit is more highly resistant to dielectric breakdown than the structure of the transistor for the input circuit.

Inventors

  • 👤 Yoshio Shintani
  • 👤 Mikio Inatsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 09:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W72/00; H10W72/90

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 115 words
A semiconductor device comprising: a semiconductor pellet; an internal cell array constituted by arranging a plurality of basic cells formed on said semiconductor pellet; input/output cells, for input/output buffer circuits, disposed in the outer peripheral direction of said internal cell array and each of said input/output cells having a first cell and a second cell, said first cell having first MISFETs for forming an input circuit, said second cell having second MISFETs for forming an output circuit; external terminals disposed in such a manner as to correspond to said input/output cells and to be positioned more outward than said input/output cells; and an amplification circuit portion of an oscillation circuit constituted by said second MISFETs.
Claim 2
Dependent Claim 115 words
A semiconductor device comprising: a semiconductor pellet; an internal cell array constituted by arranging a plurality of basic cells formed on said semiconductor pellet; input/output cells, for input/output buffer circuits, disposed in the outer peripheral direction of said internal cell array and each of said input/output cells having a first cell and a second cell, said first cell having first MISFETs for forming an input circuit, said second cell having second MISFETs for forming an output circuit; external terminals disposed in such a manner as to correspond to said input/output cells and to be positioned more outward than said input/output cells; and an amplification circuit portion of an oscillation circuit constituted by said second MISFETs.
Claim 3
Dependent Claim 19 words
A semiconductor device according to claim 1, wherein said second MISFET has greater driving capacity than said first MISFET.
Claim 4
Dependent Claim 22 words
A semiconductor device according to claim 2, wherein said second MISFET has a greater ratio of a gate-width/gate-length than said first MISFET.
Claim 5
Dependent Claim 27 words
A semiconductor device according to claim 3, wherein said second MISFETs comprise P-channel MISFETs and N-channel MISFETs, and said first MISFETs comprise P-channel MISFETs and N-channel MISFETs.
Claim 6
Dependent Claim 25 words
A semiconductor device according to claim 4, wherein said amplification circuit portion of the oscillation circuit comprises an inverter circuit constituted by said second MISFETs.
Claim 7
Dependent Claim 32 words
A semiconductor device according to claim 5, wherein said oscillation circuit comprises two adjacent input/output cells, the external terminals corresponding to said two input/output cells, and protective resistors of said input/output cells.
Claim 8
Dependent Claim 18 words
A semiconductor device according to claim 6, wherein said semiconductor device is fabricated by a master slice system.
Claim 9
Dependent Claim 16 words
A semiconductor device according to claim 7, wherein said basic cell is a CMOS type cell.
Claim 10
Dependent Claim 56 words
A semiconductor device according to claim 6, wherein capacitors, disposed outside said pellet, are electrically connected in series, respectively, between a reference potential and said external terminals, and a resistor and a quartz for positive feedback, disposed outside said pellet, are electrically connected in parallel between said external terminals so as to form the oscillation circuit.
Claim 11
Dependent Claim 15 words
A semiconductor device according to claim 9, wherein said external terminal is a bonding pad.
Claim 12
Dependent Claim 30 words
A semiconductor device according to claim 6, wherein said protective resister is disposed between a first cell of the input/output cell and the external terminals corresponding to said input/output cell.
Claim 13
Dependent Claim 118 words
A semiconductor device comprising: a semiconductor pellet; an internal cell array constituted by arranging a plurality of basic cells formed on said semiconductor pellet; input/output cells, for input/output buffer circuits, disposed in the outer peripheral direction of said internal cell array and each of said input/output cells having a first cell and a second cell, said first cell having first bipolar transistors for forming an input circuit, said second cell having second bipolar transistors for forming an output circuit; external terminals disposed in such a manner as to correspond to said input/output cells and to be positioned more outward than said input/output cells; and an amplification circuit portion of an oscillation circuit constituted by said second bipolar transistors.
Claim 14
Dependent Claim 118 words
A semiconductor device comprising: a semiconductor pellet; an internal cell array constituted by arranging a plurality of basic cells formed on said semiconductor pellet; input/output cells, for input/output buffer circuits, disposed in the outer peripheral direction of said internal cell array and each of said input/output cells having a first cell and a second cell, said first cell having first bipolar transistors for forming an input circuit, said second cell having second bipolar transistors for forming an output circuit; external terminals disposed in such a manner as to correspond to said input/output cells and to be positioned more outward than said input/output cells; and an amplification circuit portion of an oscillation circuit constituted by said second bipolar transistors.
Claim 15
Dependent Claim 21 words
A semiconductor device according to claim 12, wherein said second bipolar transistor has greater driving capacity than said first bipolar transistor.
Claim 16
Dependent Claim 33 words
A semiconductor device according to claim 18, wherein said second bipolar transistors comprise NPN bipolar transistors and PNP bipolar transistors, and said first bipolar transistors comprise NPN bipolar transistors and PNP bipolar transistors.
Claim 17
Dependent Claim 26 words
A semiconductor device according to claim 14, wherein said amplification circuit portion of the oscillation circuit comprises an inverter circuit constituted by said second bipolar transistors.
Claim 18
Dependent Claim 32 words
A semiconductor device according to claim 15, wherein said oscillation circuit comprises two adjacent input/output cells, the external terminals corresponding to said two input/output cells, and protective resistors of said input/output cells.
Claim 19
Dependent Claim 18 words
A semiconductor device according to claim 16, wherein said semiconductor device is fabricated by a master slice system.

References Cited (Backward Citations)

US4893168A Cited
US4766475A Cited
US4682202A Cited
US4668972A Cited
US4682201A Cited
US4903093A Cited
US4920398A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-05-27 1994-11-26 1995-05-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-05-27 1998-11-26 1999-05-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-05-27 2002-11-26 2003-05-28 $7700.00 Window Closed / Lapsed

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