Integrated circuit driver for serial bus having output overvoltage protection

Claim 2

An integrated circuit driver for high and low lines in a bus comprising: first and second current sources connected to high and low voltage sources, respectively; and first and second means for blocking voltage spikes higher or lower than the voltages provided by said high and low voltage sources; wherein said first current source and said first blocking means are series connected between said high voltage supply and said high line, and said second current source and said second blocking means are series connected between said low voltage source and said low line.

Claim 3

The driver of claim 1 wherein said integrated circuit has a substrate of a first conductivity type, and wherein said first and second blocking means include first and second transistors, respectively, of said first conductivity type constructed in said substrate in a well of a second conductivity type.

Claim 4

The driver of claim 2 wherein said first blocking means further includes a third transistor of said second conductivity type constructed in said substrate and electrically connected to said first transistor.

Claim 5

The driver of claim 3 wherein said first and third transistors are MOSFET transistors.

Claim 6

The driver of claim 4 wherein the drain of said first transistor is connected to said high line, the well tie of said first transistor is connected to the source of said third transistor, the source of said first transistor is connected with the drain of said third transistor to said first current source, the gate of said third transistor is connected to a first voltage source and the substrate tie of said third transistor is connected to a second voltage source.

Claim 7

The driver of claim 5 wherein said first transistor is a PMOS transistor and said third transistor is an NMOS transistor.

Claim 8

The driver of claim 5 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 9

The driver of claim 5 wherein the gate of said first transistor is connected to a control line for receiving a data signal.

Claim 10

The driver of claim 2 wherein said second blocking means further includes a third transistor of said first conductivity type, constructed in said substrate in a well of said second conductivity type, and electrically connected to said second transistor.

Claim 11

The driver of claim 9 wherein said second and third transistors are MOSFET transistors.

Claim 12

The driver of claim 10 wherein the source of said second transistor is connected to said low line, the drain of said second transistor is connected to said second current source, the well tie of said second transistor is connected to the drain of said third transistor, the source of said third transistor is connected to said low line, the well tie of said third transistor is connected to a first voltage source through a biasing means, and the gate of said third transistor is connected to a second voltage source.

Claim 13

The driver of claim 11 wherein said second and third transistors are PMOS transistors.

Claim 14

The driver of claim 11 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 15

The driver of claim 11 wherein the gate of said second transistor is connected to a control line for receiving a data signal.

Claim 16

The driver of claim 11 wherein said second blocking means further includes a fourth transistor of said second conductivity type constructed in said substrate and electrically connected to the well tie of said third transistor.

Claim 17

The driver of claim 15 wherein said fourth transistor is a MOSFET transistor.

Claim 18

The driver of claim 16 wherein the source of said fourth transistor is connected to the well tie of said third transistor, the gate and drain of said fourth transistor are connected to said first voltage source, and the substrate tie of said fourth transistor is connected to said second voltage source.

Claim 19

The driver of claim 17 wherein said second and third transistors are PMOS transistors and said fourth transistor is an NMOS transistor.

Claim 20

The driver of claim 17 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 21

The driver of claim 17 wherein said second blocking means further includes a fifth transistor of said first conductivity type, constructed in said substrate in a well of said second conductivity type, and electrically connected to the source of said fourth transistor.

Claim 22

The driver of claim 20 wherein said fifth transistor is a MOSFET transistor.

Claim 23

The driver of claim 21 wherein the drain of said fifth transistor is connected to the source of said fourth transistor, the well tie and drain of said fifth transistor are connected, the source of said fifth transistor is connected to said first voltage source, and the gate of said fifth transistor is resistively connected to said low line.

Claim 24

The driver of claim 22 wherein said second, third and fifth transistors are PMOS transistors and said fourth transistor is an NMOS transistor.

Claim 25

The driver of claim 23 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 26

The driver of claim 22 wherein the gate of said fifth transistor is connected to said low line by first and second resistors series connected between the gate of said fifth transistor and said low line, and wherein said high line is connected to the common point between said first and second resistors.

Claim 27

The driver of claim 2 wherein said first and second blocking means include a third transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, said third transistor being connected between said high line and the control electrodes of said first and second transistors.

Claim 28

The driver of claim 26 wherein said first, second and third transistors are MOSFET transistors.

Claim 29

The driver of claim 27 wherein the source of said first transistor is connected to said first current source, the drain of said first transistor is connected to said high line, the source of said second transistor is connected to said low line, the drain of said second transistor is connected to said second current source, the source of said third transistor is connected to said high line, the drain of said third transistor is connected to the gates of said first and second transistors, and the gate of said third transistor is connected to biasing means.

Claim 30

The driver of claim 28 wherein said first, second and third transistors are PMOS transistors.

Claim 31

The driver of claim 28 wherein the gates of said first and second transistors are also connected to a control line for receiving a data signal.

Claim 32

The driver of claim 28 wherein said biasing means includes a fourth transistor of said second conductivity type constructed in said substrate and connected between a first voltage source and the gate of said third transistor.

Claim 33

The driver of claim 31 wherein said fourth transistor is a MOSFET transistor.

Claim 34

The driver of claim 32 wherein the drain and gate of said fourth transistor are connected to a first voltage source and the source of said third transistor is connected to the gate of said third transistor.

Claim 35

The driver of claim 33 wherein said third transistor is an NMOS transistor.

Claim 36

The driver of claim 33 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 37

The driver of claim 33 wherein said biasing means further includes a resistor connected between the gate of said second transistor and a second voltage source.

Claim 38

The driver of claim 33 wherein the gate of said third transistor is connected to a line for receiving a reset signal.

Claim 39

The driver of claim 1, wherein said first and second current sources include first and second transistors, respectively, said driver further comprising: a current path including third, fourth and fifth transistors serially connected between said high and low voltage sources; wherein the control electrodes of said first and third transistors are connected, and the control electrodes of said second and fifth transistors are connected.

Claim 40

The driver of claim 38 wherein said first and third transistors are of a first conductivity type and are dimensionally matched and constructed proximate each other on said integrated circuit, and wherein said second and fifth transistors are of a second conductivity type and are dimensionally matched and constructed proximate each other on said integrated circuit.

Claim 41

The driver of claim 39 wherein said first, second, third and fifth transistors are LDD MOSFET transistors.

Claim 42

The driver of claim 40 wherein: said first and third transistors are laid out side by side on said integrated circuit so that the drain of one transistor faces the source of the other transistor; and said second and fifth transistors are laid out side by side on said integrated circuit so that the drain of one transistor faces the source of the other.

Claim 43

The driver of claim 41 wherein said first and third transistors are PMOS transistors and said second and fifth transistors are NMOS transistors, and wherein the source of said first and third transistors are connected to said high voltage source and the source of said second and fifth transistors are connected to said low voltage source.

Claim 44

The driver of claim 42 further comprising: a capacitor connected between the gate of said second transistor and said low voltage source to match the gate capacitance of said second and firth transistors with the gate capacitance of said first and third transistors.

Claim 45

The driver of claim 38 further comprising: a first resistor connected between the gate of said first transistor and said high voltage source; and a second resistor connected between the gate of said second transistor and said low voltage source.

Claim 46

The driver of claim 38 wherein the gate of said fourth transistor is connected to a control line for receiving a data signal.

Claim 47

The driver of claim 42 wherein the gates of said first and third transistors are connected to the drain of said third transistor and the gates of said second and fifth transistors are connected to the drain of said fifth transistor.

Claim 48

The driver of claim 38 further comprising: a first resistor and sixth transistor series connected between the gate of said first transistor and said high voltage source; and a second resistor and seventh transistor series connected between the gate of said second transistor and said low voltage source.

Claim 49

The driver of claim 47 wherein the gate of each of said sixth and seventh transistors is connected to a control circuit for turning said transistors off during operation of said first and second current sources.

Claim 50

The driver of claim 2 wherein: said first blocking means includes a third transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, said third transistor being connected between said high line and the control electrode of said first transistor; and said second blocking means includes a fourth transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, said fourth transistor being connected between said low line and the control electrode of said second transistor.

Claim 51

The driver of claim 49 wherein said first, second, third and fourth transistors are MOSFET transistors.

Claim 52

The driver of claim 49 wherein the source of said first transistor is connected to said first current source, the drain of said first transistor is connected to said high line, the source of said second transistor is connected to said low line, the drain of said second transistor is connected to said second current source, the source of said third transistor is connected to said high line, the drain of said third transistor is connected to the gate of said first transistor, the gate of said third transistor is connected to biasing means, the source of said fourth transistor is connected to said low line, the drain of said fourth transistor is resistively connected to the gate of said first transistor, and the gate of said fourth transistor is connected to said high voltage source.

Claim 53

The driver of claim 51 wherein said first, second, third and fourth transistors are PMOS transistors.

Claim 54

The driver of claim 52 wherein said biasing means includes a fifth transistor and resistor, said fifth transistor being a PMOS transistor with its source and well tie connected to said high voltage source, its gate connected to said low voltage source, its drain connected to the gate of said third transistor, and said resistor being connected between the drain of said fifth transistor and said low voltage source.

Claim 55

An integrated circuit driver, formed in a substrate of a first conductivity type, for high and low lines in a bus comprising: first and second current sources connected to high and low voltage sources, respectively; and first and second means for blocking voltage spikes higher or lower than the voltages provided by said high and low voltage sources; wherein said first current source and said first blocking means are series connected between said high voltage supply and said high line, and said second current source and said second blocking means are series connected between said low voltage source and said low line; wherein said first blocking means includes a first MOSFET transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, and a second MOSFET transistor of said second conductivity type constructed in said substrate, said first transistor being series connected with said first current source and said second transistor being connected to the well tie of said first transistor; wherein said second blocking means includes third, fourth and fifth MOSFET transistors of said first conductivity type, constructed in said substrate in respective wells of said second conductivity type, and a sixth MOSFET transistor of said second conductivity type constructed in said substrate, said third transistor being series connected with said second current source, said fourth transistor being connected to the well tie of said second transistor, and said fifth and sixth transistors being connected to the well tie of said fourth transistor; and wherein said first and second blocking means further include a seventh MOSFET transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, and a eighth MOSFET transistor of said second conductivity type constructed in said substrate, said seventh transistor being connected between said high line and PG,29 the control electrodes of said first and third transistors, and said eighth transistor being connected to the gate of said eighth transistor.

Claim 56

An integrated circuit driver, formed in a substrate of a first conductivity type, for high and low lines in a bus comprising: first and second current sources connected to high and low voltage sources, respectively; and first and second means for blocking voltage spikes higher or lower than the voltages provided by said high and low voltage sources; wherein said first current source and said first blocking means are series connected between said high voltage supply and said high line, and said second current source and said second blocking means are series connected between said low voltage source and said low line; wherein said first blocking means includes a first MOSFET transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, and a second MOSFET transistor of said second conductivity type constructed in said substrate, said first transistor being series connected with said first current source and said second transistor being connected to the well tie of said first transistor; wherein said second blocking means includes third, fourth and fifth MOSFET transistors of said first conductivity type, constructed in said substrate in respective wells of said second conductivity type, and a sixth MOSFET transistor of said second conductivity type constructed in said substrate, said third transistor being series connected with said second current source, said fourth transistor being connected to the well tie of said second transistor, and said fifth and sixth transistors being connected to the well tie of said fourth transistor; and wherein said first and second blocking means further include a seventh MOSFET transistor of said first conductivity type constructed in said substrate in a well of a second conductivity type, and a eighth MOSFET transistor of said second conductivity type constructed in said substrate, said seventh transistor being connected between said high line and PG,29 the control electrodes of said first and third transistors, and said eighth transistor being connected to the gate of said eighth transistor.

Claim 57

The driver of claim 54 wherein the drain of said first transistor is connected to said high line, the well tie of said first transistor is connected to the source of said second transistor, the source of said first transistor is connected with the drain of said second transistor to said first current source, the gate of said second transistor is connected to a first voltage source, the substrate tie of said second transistor is connected to a second voltage source, the source of said third transistor is connected to said low line, the drain of said third transistor is connected to said second current source, the well tie of said third transistor is connected to the drain of said fourth transistor, the source of said fourth transistor is connected to said low line, the well tie of said fourth transistor is connected to the source of said sixth transistor, the gate of said fourth transistor is connected to said second voltage source, the source of said sixth transistor is connected to the drain of said fifth transistor, the gate and drain of said sixth transistor are connected to said first voltage source, the substrate tie of said sixth transistor is connected to said second voltage source, the well tie and drain of said fifth transistor are connected, the source of said fifth transistor is connected to said first voltage source, the gate of said fifth transistor is connected to said low line, the source of said seventh transistor is connected to said high line, the drain of said seventh transistor is connected to the gates of said first and third transistors, the gate of said seventh transistor is connected to the source of said eighth transistor, and the drain and gate of said eighth transistor are connected to said first voltage source.

Claim 58

The driver of claim 55 wherein said first, third, fourth, fifth and seventh transistors are PMOS transistors and said second, sixth and eighth transistors are NMOS transistors.

Claim 59

The driver of claim 56 wherein said first voltage source is said high voltage source and said second voltage source is said low voltage source.

Claim 60

The driver of claim 57 wherein the gates of said first and third transistors are connected to a control line for receiving a data signal, and the gate of said seventh transistor is connected to a line for receiving a reset signal.

Claim 61

The driver of claim 58 wherein the gate of said fifth transistor is connected to said low line by first and second resistors series connected between the gate of said fifth transistor and said low line, wherein said high line is connected to the common point between said first and second resistors, and the gate of said seventh transistor is connected to said low voltage source by a third resistor.

Claim 62

An integrated circuit driver for high and low lines in a bus comprising: first and second current sources connected to high and low voltage sources, respectively; control means for turning said current sources on and off; and first and second means for controlling current flow between said first and second current sources and said said high and low lines, respectively, and for blocking voltage spikes higher or lower than the voltages provided by said high and low voltage sources; wherein said first current source and said first means are series connected between said high voltage supply and said high line, and said second current source and said second means are series connected between said low voltage source and said low line; and wherein said control means is connected to said first and second current sources.

Claim 63

An integrated circuit driver for high and low lines in a bus comprising: first and second current sources connected to high and low voltage sources, respectively; control means for turning said current sources on and off; and first and second means for controlling current flow between said first and second current sources and said said high and low lines, respectively, and for blocking voltage spikes higher or lower than the voltages provided by said high and low voltage sources; wherein said first current source and said first means are series connected between said high voltage supply and said high line, and said second current source and said second means are series connected between said low voltage source and said low line; and wherein said control means is connected to said first and second current sources.

Claim 64

The driver of claim 60, further comprising: means for selectively enabling each of said control means and said first and second means.

Claim 65

The driver of claim 61 wherein said first means includes a first transistor, said second means includes a second transistor, and said control means includes a third transistor.

Claim 66

The driver of claim 62 wherein said enabling means includes: means for timing when each of said first second and third transistors is turned on and off; and rate control means for controlling the rate at which each of said first and second transistors is turned on and off.

Claim 67

The driver of claim 63 wherein said timing means includes: a series RC circuit responsive to a data signal and having a plurality of tap points; first and second selector circuits connected between respective ones of said tap points and said rate control means; and a third selector circuit connected between at least one of said tap points and the control electrode of said third transistor.

Claim 68

The driver of claim 64 wherein said rate control means includes: a first resistive circuit, series connected with a fourth transistor between said high and low voltage sources, having a tap point connected to the control electrode of said first transistor for providing a first control voltage thereto; and a second resistive circuit, series connected with a fifth transistor between said high and low voltage sources, having a tap point resistively connected to the control electrode of said second transistor for providing a second control voltage thereto; wherein the control electrode of said fourth transistor is connected to said first selector circuit, and the control electrode of said fifth transistor is connected to said second selector circuit.

Claim 69

The driver of claim 64 wherein said series RC circuit includes a plurality of resistors connected at respective ones of said tap points; each of said first, second and third selector circuits has a pair of complementary transistors; and each of said transistors in said selector circuits is connected to a respective one of said tap points.