Data transmission system

Claim 2

A data transmission system comprising: first and second buses; first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; supply means connected to said buses for precharging said buses to a first voltage level; and circuit means connecting said buses and responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus.

Claim 3

The data transmission system of claim 1 further comprising a control line connected to said supply means, wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line.

Claim 4

The data transmission system of claim 2 further comprising: first and second power supply terminals at said first and second voltage levels, respectively, wherein said supply means comprises switch means responsive to said control signal for connecting said first power supply terminal to said buses.

Claim 5

The data transmission system of claim 3 wherein said switch means comprise: a first transistor connected between said first power supply terminal and said first bus; and a second transistor connected between said first power supply terminal and said second bus, wherein the control electrode of each of said transistors is connected to said control line.

Claim 6

The data transmission system of claim 4 wherein said first and second transistors are NMOS field effect transistors.

Claim 7

The data transmission system of claim 3 wherein said circuit means comprises: a NAND gate with first and second input lines connected to said first and second buses, respectively, and an output line for controlling the connection of said buses to said second power supply terminal when said data signal is at said second level and said control signal is at said second value.

Claim 8

The data transmission system of claim 6 further comprising a first inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal.

Claim 9

The data transmission system of claim 7 wherein said first inverter is a CMOS inverter which includes third and fourth series connected transistors with said third transistor being a PMOS field effect transistor and said fourth transistor being an NMOS field effect transistor.

Claim 10

The data transmission system of claim 7 wherein said circuit means further comprises: a fifth transistor connecting said circuit means to said second power supply terminal; and a sixth transistor connecting said circuit means to said second power supply terminal; wherein the control electrode of each of said fifth and sixth transistors is connected to said output line of said first inverter.

Claim 11

The data transmission system of claim 9 wherein said fifth and sixth transistors are NMOS field effect transistors.

Claim 12

The data transmission system of claim 9 wherein said circuit means further comprises: seventh and eighth transistors, said seventh transistor being connected between said first bus and said fifth transistor, said eighth transistor being connected between said second bus and said sixth transistor, and the control electrodes of said seventh and eight transistors being connected to said NAND gate output line.

Claim 13

The data transmission system of claim 11 wherein said seventh and eighth transistors are NMOS field effect transistors.

Claim 14

The data transmission system of claim 11 wherein said NAND gate includes ninth and tenth PMOS field effect transistors and eleventh and twelfth NMOS field effect transistors wherein: said ninth transistor is connected between said first power supply terminal and said NAND gate output line with its gate connected to said first data bus; said tenth transistor is connected between said first power supply and said NAND gate output line with its gate connected to said second data bus; and said eleventh and twelfth transistors are series connected between said NAND gate output line and said second power supply terminal with the gate of said eleventh transistor being connected to said second data bus and the gate of said twelfth transistor being connected to said first data bus.

Claim 15

The data transmission system of claim 3 wherein said circuit means comprises: a first inverter, a first transfer gate and a first transistor, wherein the input to said first inverter is connected to said first bus, the output of said first inverter is connected to the input of said first transfer gate, the output of said first transfer gate is connected to the control electrode of said first transistor and said first transistor is connected between said second bus and said second power supply terminal; and a second inverter, a second transfer gate and a second transistor, wherein the input to said second inverter is connected to said second bus, the output of said second inverter is connected to the input of said second transfer gate, the output of said second transfer gate is connected to the control electrode of said second transistor, and said second transistor is connected between said first bus and said second power supply terminal.

Claim 16

The data transmission system of claim 14 wherein said first and second inverters are each CMOS inverters and wherein: said first inverter includes a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; and said second inverter includes a fifth PMOS field effect transistor and an sixth NMOS field effect transistor connected in series between said first and second power supply terminals.

Claim 17

The data transmission system of claim 14 wherein said circuit means further comprises third and fourth transistors wherein: said third transistor is connected between the output of said first transfer gate and said second power supply terminal with its control electrode receiving said control signal; and said fourth transistor is connected between the output of said second transfer gate and said second power supply terminal with its control electrode receiving said control signal.

Claim 18

The data transmission system of claim 16 wherein said third and fourth transistors are NMOS field effect transistors.

Claim 19

The data transmission system of claim 14 wherein each of said first and second transfer gates is a PN channel combination gate.

Claim 20

The data transmission system of claim 18 wherein: said first transfer gate includes a third NMOS field effect transistor connected in parallel with a fourth PMOS field effect transistor; said second transfer gate includes an fifth NMOS field effect transistor connected in parallel with a sixth PMOS field effect transistor; the gates of said third and fifth transistors receive a complementary control signal; and the gates of said fourth and sixth transistors receive said control signal.

Claim 21

The data transmission system of claim 19 further comprising a third inverter having an input line for receiving said control signal and an output line for providing said complementary control signal, said input line being connected to said control line and said output line being connected to the gates of said third and fifth transistors.

Claim 22

The data transmission system of claim 20 wherein said third inverter is a CMOS inverter which includes seventh and eighth series connected transistors with said seventh transistor being a PMOS field effect transistor and said eighth transistor being an NMOS field effect transistor.

Claim 23

The data transmission system of claim 14 wherein each of said first and second transfer gates is an N channel gate.

Claim 24

The data transmission system of claim 22 wherein: said first transfer gate includes a third transistor; said second transfer gate includes a fourth transistor; and the control electrodes of said third and fourth transistors receive a complementary control signal.

Claim 25

The data transmission system of claim 23 wherein said third and fourth transistors are NMOS field effect transistors.

Claim 26

The data transmission system of claim 23 further comprising a CMOS inverter having an input line for receiving said control signal and an output line for providing said complementary control signal, said output line being connected to the gates of said third and fourth transistors.

Claim 27

The data transmission system of claim 14 wherein each of said first and second transfer gates is a P channel gate.

Claim 28

The data transmission system of claim 26 wherein: said first transfer gate includes a third transistor; said second transfer gate includes a fourth transistor; and the control electrodes of said third and fourth transistors receive said control signal.

Claim 29

The data transmission system of claim 27 wherein said third and fourth transistors are PMOS field effect transistors and the gates of said transistors are connected to said control line.

Claim 30

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a NAND gate with first and second input lines connected to said first and second buses, respectively, and an output line for connecting said buses to said second power supply terminal when said data signal is at said second level and said control signal is at said second value, wherein said NAND gate includes third and fourth PMOS field effect transistors and fifth and sixth NMOS field effect transistors wherein: said third transistor is connected between said first power supply terminal and said NAND gate output line with its gate connected to said first data bus; said fourth transistor is connected between said first power supply and said NAND gate output line with its gate connected to said second data bus; and said fifth and sixth transistors are series connected between said NAND gate output line and said second power supply terminal with the gate of said fifth transistor being connected to said second data bus and the gate of said sixth transistor being connected to said first data bus; ii. seventh and eighth NMOS transistors connecting said circuit means to said second power supply terminal wherein the gate of each of said seventh and eighth transistors is connected to said output line of said first inverter; iii. ninth and tenth NMOS transistors, said ninth transistor being connected between said first bus and said seventh transistor, said tenth transistor being connected between said second bus and said eighth transistor, and the gates of said ninth and tenth transistors being connected to said NAND gate output line.

Claim 31

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a NAND gate with first and second input lines connected to said first and second buses, respectively, and an output line for connecting said buses to said second power supply terminal when said data signal is at said second level and said control signal is at said second value, wherein said NAND gate includes third and fourth PMOS field effect transistors and fifth and sixth NMOS field effect transistors wherein: said third transistor is connected between said first power supply terminal and said NAND gate output line with its gate connected to said first data bus; said fourth transistor is connected between said first power supply and said NAND gate output line with its gate connected to said second data bus; and said fifth and sixth transistors are series connected between said NAND gate output line and said second power supply terminal with the gate of said fifth transistor being connected to said second data bus and the gate of said sixth transistor being connected to said first data bus; ii. seventh and eighth NMOS transistors connecting said circuit means to said second power supply terminal wherein the gate of each of said seventh and eighth transistors is connected to said output line of said first inverter; iii. ninth and tenth NMOS transistors, said ninth transistor being connected between said first bus and said seventh transistor, said tenth transistor being connected between said second bus and said eighth transistor, and the gates of said ninth and tenth transistors being connected to said NAND gate output line.

Claim 32

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth NMOS field effect transistor connected in parallel with a sixth PMOS field effect transistor with the gate of said fifth transistor receiving a complementary control signal and the gate of said sixth transistor receiving said control signal; iii. a seventh transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said seventh transistor; iv. a third inverter including a eighth PMOS field effect transistor and an ninth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a tenth NMOS field effect transistor connected in parallel with a eleventh PMOS field effect transistor with the gate of said tenth transistor receiving a complementary control signal and the gate of said eleventh transistor receiving said control signal; vi. a twelfth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said twelfth transistor; vii. a thirteenth NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a fourteenth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 33

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth NMOS field effect transistor connected in parallel with a sixth PMOS field effect transistor with the gate of said fifth transistor receiving a complementary control signal and the gate of said sixth transistor receiving said control signal; iii. a seventh transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said seventh transistor; iv. a third inverter including a eighth PMOS field effect transistor and an ninth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a tenth NMOS field effect transistor connected in parallel with a eleventh PMOS field effect transistor with the gate of said tenth transistor receiving a complementary control signal and the gate of said eleventh transistor receiving said control signal; vi. a twelfth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said twelfth transistor; vii. a thirteenth NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a fourteenth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 34

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth NMOS field effect transistor with its gate receiving a complementary control signal; iii. a sixth transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said sixth transistor; iv. a third inverter including a seventh PMOS field effect transistor and an eighth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a ninth NMOS field effect transistor with its gate receiving a complementary control signal; vi. a tenth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said tenth transistor; vii. a eleventh NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a twelfth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 35

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; f. a first CMOS inverter having an input line connected to said control line for receiving said control signal and an output line connected to said circuit means for providing a complementary control signal; and g. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth NMOS field effect transistor with its gate receiving a complementary control signal; iii. a sixth transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said sixth transistor; iv. a third inverter including a seventh PMOS field effect transistor and an eighth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a ninth NMOS field effect transistor with its gate receiving a complementary control signal; vi. a tenth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said tenth transistor; vii. a eleventh NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a twelfth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 36

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; and f. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth PMOS field effect transistor with its gate receiving said control signal; iii. a sixth transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said sixth transistor; iv. a third inverter including a seventh PMOS field effect transistor and an eighth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a ninth PMOS field effect transistor with its gate receiving said control signal; vi. a tenth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said tenth transistor; vii. a eleventh NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a twelfth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 37

A data transmission system comprising: a. first and second buses; b. first and second means attached to said first and second buses, respectively, for the transfer of data signals to said buses; c. first and second power supply terminals at said first and second voltage levels, respectively; d. supply means for precharging said first and second buses to a first voltage level wherein said supply means comprises: i. a first NMOS field effect transistor connected between said first power supply terminal and said first bus; and ii. a second NMOS field effect transistor connected between said first power supply terminal and said second bus; e. a control line connected to said supply means wherein said supply means is responsive to a first value of a digital control signal on said control line and said circuit means is responsive to a second value of said control signal on said control line, and wherein the gate of each of said first and second transistors is connected to said control line; and f. circuit means responsive to a data signal at a second voltage level on either of said buses for transferring said signal to the other bus, said circuit means comprising: i. a second inverter including a third PMOS field effect transistor and a fourth NMOS field effect transistor connected in series between said first and second power supply terminals; ii. a first transfer gate including a fifth PMOS field effect transistor with its gate receiving said control signal; iii. a sixth transistor connected between said second bus and said second power supply terminal, wherein the input to said second inverter is connected to said first bus, the output of said second inverter is connected to the input of said first transfer gate, and the output of said first transfer gate is connected to the control electrode of said sixth transistor; iv. a third inverter including a seventh PMOS field effect transistor and an eighth NMOS field effect transistor connected in series between said first and second power supply terminals; v. a second transfer gate including a ninth PMOS field effect transistor with its gate receiving said control signal; vi. a tenth transistor connected between said first bus and said second power supply terminal, wherein the input to said third inverter is connected to said second bus, the output of said third inverter is connected to the input of said second transfer gate, and the output of said second transfer gate is connected to the control electrode of said tenth transistor; vii. a eleventh NMOS field effect transistor connected between the output of said first transfer gate and said second power supply terminal with its gate receiving said control signal; and viii. a twelfth NMOS field effect transistor connected between the output of said second transfer gate and said second power supply terminal with its gate receiving said control signal.

Claim 38

The data transmission system according to claims 1, 29, 30, 31 or 32 wherein said first voltage level is high relative to said second voltage level.