Output circuit of semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit comprising: an output circuit including a transistor whose conduction state is controlled according to an internal signal and charging and discharging a preset node by controlling the conduction state of said transistor, thus outputting a signal; and control means for increasing a rate of reduction in the conduction resistance of said transistor for a preset period of time after the control signal has changed in level.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said output circuit includes a signal output terminal; a first output section operated after the level of the control signal is changed, and charging and discharging said output terminal according to the internal signal to output a corresponding signal; and a second output section operated only in a preset period of time after the level of the control signal is changed, and charging and discharging said output terminal according to the internal signal to output a corresponding signal; and the power source sections for the buffer transistors of said first and second output sections are separated from each other.

Claim 4

A semiconductor integrated circuit comprising: a data output circuit including a transistor whose conduction state is controlled according to readout data and charging and discharging a preset node at a predetermined rate by controlling the conduction state of said transistor, thus outputting memory cell data; and control means for charging or discharging the preset node of said data output circuit at a rate different from the predetermined rate for a preset period of time after an output enable signal has changed in level.

Claim 5

A semiconductor integrated circuit comprising: a data output circuit including a transistor whose conduction state is controlled according to readout data and charging and discharging a preset node at a predetermined rate by controlling the conduction state of said transistor, thus outputting memory cell data; and control means for charging or discharging the preset node of said data output circuit at a rate different from the predetermined rate for a preset period of time after an output enable signal has changed in level.

Claim 6

A semiconductor integrated circuit according to claim 3, wherein said output circuit includes a data output terminal; a first data output section operated after the level of the enable signal is changed, and charging and discharging said output terminal according to the internal data to output a corresponding signal; and a second data output section operated only in a preset period of time after the level of the enable signal is changed, and charging and discharging said output terminal according to the internal data to output a corresponding signal; and the power source sections for the buffer transistors of said first and second data output sections are separated from each other.

Claim 7

A semiconductor integrated circuit comprising: an output circuit including an output node and at least two output transistors each having a drain, a source, and a gate, one of said transistors charges the output node, and the other of said transistors discharges the output node; and control means for changing the speed at which the potential of the gate of at least one of said output transistors varies.

Claim 8

A semiconductor integrated circuit comprising: an output circuit including an output node and at least two output transistors each having a drain, a source, and a gate, one of said transistors charges the output node, and the other of said transistors discharges the output node; and control means for changing the speed at which the potential of the gate of at least one of said output transistors varies.

Claim 9

A semiconductor integrated circuit according to claim 5, wherein said control means includes a switching transistor for charging or discharging the gates of said output transistors, and said speed is changed by changing the effective channel width of the switching transistor.

Claim 10

A semiconductor integrated circuit according to claim 6, wherein said switching transistor is replaced by a plurality of switching transistors, and the number of said switching transistors which are simultaneously used to charge or discharge the gate of said output transistor, thereby to change said effective channel width.

Claim 11

A semiconductor integrated circuit according to claim 6 or 7, wherein said control means includes pulse signal generating means for generating a pulse signal when a control signal changes to a higher level or a lower level, and the pulse signal is used to change said effective channel width.

Claim 12

A semiconductor integrated circuit according to claim 8, wherein said control means turns off said output transistor when said control signal at a first logic level, and turns on said output transistor when said control signal rises or falls from said first logic level.

Claim 13

A semiconductor integrated circuit according to claim 5, wherein said output circuit includes a first transistor of a first channel type having a current path connected between said output node and a first potential-applying means, and a second transistor of a second channel type having a current path connected between said output node and a second potential-applying means; and said control means includes first charging/discharging control means for charging or discharging a first node connected to the gate of said first transistor, after the level of said control signal has changed, in accordance with detection data and inverting an internal enable signal, second charging/discharging control means for charging or discharging a second node connected to the gate of said second transistor, after the level of said control signal has changed, in accordance with the detection data and the internal enable signal, discharging control means for discharging said first node in accordance with the detecting data and a pulse signal during a predetermined period after the level of said control signal has changed, and charging control means for charging said second node in accordance with the detecting data and a signal obtained by inverting the pulse signal, during said predetermined period.

Claim 14

A semiconductor integrated circuit according to claim 10, wherein said internal enable signal, the inverted internal enable signal, the pulse signal, and the inverted pulse signal are generated in accordance with said control signal.

Claim 15

A semiconductor integrated circuit according to claim 5, wherein said output transistors are of opposite channel types.

Claim 16

A semiconductor integrated circuit according to claim 5, further comprising a first potential-applying means for applying a first potential, and a second potential-applying means for applying a first potential, and wherein said control means includes a third potential-applying means for applying a third potential which is somewhere between the first and second potentials.

Claim 17

A semiconductor integrated circuit according to claim 13, wherein said control means includes a plurality of switching transistors for charging or discharging the gate of said output transistor, only some of the switching transistors are used to charge or discharge the gate of said output transistor, thereby to reduce said speed, while the remaining switching transistors charge or discharge the gate of said output transistor at said third potential.

Claim 18

A semiconductor integrated circuit according to claim 13 or 14, wherein said third potential-applying means comprises a transistor having a source connected to said first or second potential-applying means, a drain, and a gate connected to the drain.

Claim 19

A semiconductor integrated circuit according to claim 5, wherein said output circuit includes a first transistor of a first channel type having a current path connected between said output node and a first potential-applying means, and a second transistor of a second channel type having a current path connected between said output node and a second potential-applying means; and said control means includes first charging/discharging control means for charging or discharging a first node connected to the gate of said first transistor, after the level of said control signal has changed, in accordance with detection data and inverting an internal enable signal, second charging/discharging control means for charging or discharging a second node connected to the gate of said second transistor, after the level of said control signal has changed, in accordance with the detection data and the internal enable signal, a third potential-applying means for applying a potential to said first charging/discharging means, said potential being higher than the potential applied from said second potential-applying means by a predetermined value, a fourth potential-applying means for applying a potential to said second charging/discharging means, said potential being lower than the potential applied from said first potential-applying means by a predetermined value, discharging control means for discharging said first node in accordance with the detecting data and a pulse signal during a predetermined period after the level of said control signal has changed, and charging control means for charging said second node in accordance with the detecting data and a signal obtained by inverting the pulse signal, during said predetermined period.

Claim 20

A semiconductor integrated circuit according to claim 5, wherein said output circuit includes a first transistor of a first channel type having a current path connected between said output node and a first potential-applying means, and a second transistor of a second channel type having a current path connected between said output node and a second potential-applying means; and said control means includes first charging/discharging control means for charging or discharging a first node connected to the gate of said first transistor, after the level of said control signal has changed, in accordance with detection data and inverting an internal enable signal, second charging/discharging control means for charging or discharging a second node connected to the gate of said second transistor, after the level of said control signal has changed, in accordance with the detection data and the internal enable signal, a third potential-applying means for applying a potential to said first charging/discharging means, said potential being higher than the potential applied from said second potential-applying means by a value determined by the threshold voltage of a transistor, a fourth potential-applying means for applying a potential to said second charging/discharging means, said potential being lower than the potential applied from said first potential-applying means by the value determined by the threshold voltage of a transistor, discharging control means for discharging said first node in accordance with the detecting data and the pulse signal during a predetermined period after the level of said control signal has changed, and charging control means for charging said second node in accordance with the detecting data and a signal obtained by inverting the pulse signal, during said predetermined period.

Claim 21

A semiconductor integrated circuit according to claim 5, wherein said output circuit includes a first transistor of a first channel type having a current path connected between said output node and a first potential-applying means, a second transistor of a second channel type having a current path connected between said output node and a second potential-applying means, a third transistor of the first channel type having a current path connected between said output node and the first potential-applying means, and a fourth transistor of the second channel type having a current path connected between said output node and said second potential-applying means; and said control means includes first charging/discharging control means for charging or discharging a first node connected to the gate of said first transistor, after the level of said control signal has changed, in accordance with detection data and a signal obtained by inverting a first internal enable signal, second charging/discharging control means for charging or discharging a second node connected to the gate of said second transistor, after the level of said control signal has changed, in accordance with the detection data and the first internal enable signal, third charging/discharging control means for charging or discharging a third node connected to the gate of said third transistor, after the level of said control signal has changed, in accordance with the detection data and a signal obtained by inverting a second internal enable signal, fourth charging/discharging control means for charging or discharging a fourth node connected to the gate of said fourth transistor, after the level of said control signal has changed, in accordance with the detection data and the second internal enable signal, discharging control means for discharging said third node in accordance with the detecting data and the pulse signal during a predetermined period after the level of said control signal has changed, and charging control means for charging said fourth node in accordance with the detecting data and a signal obtained by inverting the pulse signal, during said predetermined period.

Claim 22

A semiconductor integrated circuit according to claim 5, wherein said output circuit includes a first transistor of a first channel type having a current path connected between said output node and a first potential-applying means, a second transistor of a second channel type having a current path connected between said output node and a second potential-applying means, a third transistor of the first channel type having a current path connected between said output node and the first potential-applying means, and a fourth transistor of the second channel type having a current path connected between said output node and said second potential-applying means; and said control means includes first charging/discharging control means for charging or discharging a first node connected to the gate of said first transistor, after the level of said control signal has changed, in accordance with detection data and a signal obtained by inverting a first internal enable signal, second charging/discharging control means for charging or discharging a second node connected to the gate of said second transistor, after the level of said control signal has changed, in accordance with the detection data and the first internal enable signal, third charging/discharging control means for charging or discharging a third node connected to the gate of said third transistor, after the level of said control signal has changed, in accordance with the detection data and a signal obtained by inverting a second internal enable signal, fourth charging/discharging control means for charging or discharging a fourth node connected to the gate of said fourth transistor, after the level of said control signal has changed, in accordance with the detection data and the second internal enable signal.

Claim 23

A semiconductor integrated circuit comprising: an output circuit including an output node, a first output section for charging the output node in response to an internal signal, and a second output section for discharging the output node, at least one of said output sections having at least two transistors each having a source-drain current path connected at one end to said output node; control means for turning off said transistors when a control signal is at a first logic level, turning on said transistors in response to the internal signal after the level of said control signal has changed from the first logic level to a second logic level, and turning off at least one of said transistors upon lapse of a predetermined period after the level of said control signal has changed from the first logic level to a second logic level, thereby to differentiate the response speeds of said transistors and/or the speeds at which the gate voltages of said transistors change.

Claim 24

A semiconductor integrated circuit comprising: an output circuit including an output node, a first output section for charging the output node in response to an internal signal, and a second output section for discharging the output node, at least one of said output sections having at least two transistors each having a source-drain current path connected at one end to said output node; control means for turning off said transistors when a control signal is at a first logic level, turning on said transistors in response to the internal signal after the level of said control signal has changed from the first logic level to a second logic level, and turning off at least one of said transistors upon lapse of a predetermined period after the level of said control signal has changed from the first logic level to a second logic level, thereby to differentiate the response speeds of said transistors and/or the speeds at which the gate voltages of said transistors change.

Claim 25

A semiconductor integrated circuit according to claim 5, 14 or 20, further comprising an array of memory cells, a row decoder and a column decoder which cooperate to select the memory cells, and data detecting circuit detecting data stored in any memory cell selected by the row and column decoders.

Claim 26

A semiconductor integrated circuit according to claim 21, wherein said control signal is generated from an output enable signal externally input to the semiconductor integrated circuit.

Claim 27

A semiconductor integrated circuit according to claim 8, further comprising an array of memory cells, a row decoder and a column decoder which cooperate to select the memory cells, and data detecting circuit detecting data stored in any memory cell selected by the row and column decoders.

Claim 28

A semiconductor integrated circuit according to claim 23, wherein said control signal is generated from an output enable signal externally input to the semiconductor integrated circuit.