US5017808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BI-MOS logic circuit having a switch circuit for discharging electrical charge accumulated in a parasitic capacitor
Assignee: Toshiba Corp
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Filing: 1990-01-30
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Granted: 1991-05-21
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Expires: 2010-01-30
Abstract
Abstract Disclosed herein is a Bi-MOS logic circuit comprising first and second NPN transistors forming an output buffer; first and second MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-latching mode; and third and fourth MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-inputting mode. The Bi-MOS logic circuit further comprises a switch circuit for discharging a parasitic capacitor located at the node of the series circuit comprised of the first and second MOS transistors.
Inventors
- 👤 Masaji Ueno
- 👤 Kumi Ofusa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/0008; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
A Bi-MOS logic circuit comprising: a first NPN transistor connected between a power-supply potential terminal and a signal-outputting terminal; a second NPN transistor connected between the signal-outputting terminal and a reference potential terminal; a load circuit connected between the power-supply potential terminal and the base of the first NPN transistor; a first series circuit connected between the base of the first NPN transistor and the base of the second NPN transistor, and including first and second MOS transistors, the first MOS transistor being controlled by a first input data signal, and the second MOS transistor being controlled a first clock signal; a second series circuit connected between the base of the first NPN transistor and the base of the second NPN transistor, and including third and fourth MOS transistors, said third MOS transistor being controlled by a second clock signal opposite in phase to the first clock signal, and the fourth MOS transistor being controlled by a second input data signal advanced in phase with respect to the first input data signal; and switching means connected between the base of the second NPN transistor and the reference potential terminal, said switching means being on when the first and second MOS transistors are off and on, respectively.
Claim 2
Dependent Claim
206 words
A Bi-MOS logic circuit comprising: a first NPN transistor connected between a power-supply potential terminal and a signal-outputting terminal; a second NPN transistor connected between the signal-outputting terminal and a reference potential terminal; a load circuit connected between the power-supply potential terminal and the base of the first NPN transistor; a first series circuit connected between the base of the first NPN transistor and the base of the second NPN transistor, and including first and second MOS transistors, the first MOS transistor being controlled by a first input data signal, and the second MOS transistor being controlled a first clock signal; a second series circuit connected between the base of the first NPN transistor and the base of the second NPN transistor, and including third and fourth MOS transistors, said third MOS transistor being controlled by a second clock signal opposite in phase to the first clock signal, and the fourth MOS transistor being controlled by a second input data signal advanced in phase with respect to the first input data signal; and switching means connected between the base of the second NPN transistor and the reference potential terminal, said switching means being on when the first and second MOS transistors are off and on, respectively.
Claim 3
Dependent Claim
20 words
The Bi-MOS logic circuit according to claim 1, wherein said switching means is turned on before said second 0MOS transistor.
Claim 4
Dependent Claim
22 words
The Bi-MOS logic circuit according to claim 1, wherein said switching means is turned on and off before said second MOS transistor.
Claim 5
Dependent Claim
40 words
The Bi-MOS logic circuit according to claim 1, wherein said switching means includes a fifth MOS transistor and a sixth MOS transistor which are connected in series between the base of said second NPN transistor and said reference potential terminal.
Claim 6
Dependent Claim
56 words
The Bi-MOS logic circuit according to claim 4, wherein said fifth MOS transistor is controlled by a third clock signal which is advanced in phase with respect to the first clock signal, and said fifth MOS transistor is controlled by a third input data signal which is opposite in phase to the first input data signal.
Claim 7
Dependent Claim
50 words
The Bi-MOS logic circuit according to claim 1, further comprising latch means for receiving the second input data signal when the first clock signal is at logic "0" level, latching and outputting the second input signal as first data signal while the first clock signal is at logic "1" level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |