US4841172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar-MOS logic circuit with high speed operation
Assignee: Toshiba Corp
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Filing: 1988-07-28
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Granted: 1989-06-20
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Expires: 2008-07-28
Abstract
Abstract A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.
Inventors
- 👤 Masaji Ueno
- 👤 Hideaki Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/0008; H03K19/0013; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
169 words
A logic circuit for supplying an output signal having a prescribed waveform and one of two levels in response to a prescribed input signal and a power source voltage, comprising: output circuit means for generating the output signal, including first and second output transistor means for alternately providing a first level output signal and a second level output signal; resistive means responsive to the power source voltage for supplying a current to the first output transistor means; current control means connected in parallel with the resistive means for controlling the current supplied to the first output transistor means, including first and second MOS transistor means for controlling the waveform of the first level output signal in accordance with the ratio of the channel length to the width of the first and second MOS transistor means; and output control means for controlling the first and second output transistor means in response to the input signal for supplying one of the first level output signal and the second level output signal.
Claim 2
Dependent Claim
169 words
A logic circuit for supplying an output signal having a prescribed waveform and one of two levels in response to a prescribed input signal and a power source voltage, comprising: output circuit means for generating the output signal, including first and second output transistor means for alternately providing a first level output signal and a second level output signal; resistive means responsive to the power source voltage for supplying a current to the first output transistor means; current control means connected in parallel with the resistive means for controlling the current supplied to the first output transistor means, including first and second MOS transistor means for controlling the waveform of the first level output signal in accordance with the ratio of the channel length to the width of the first and second MOS transistor means; and output control means for controlling the first and second output transistor means in response to the input signal for supplying one of the first level output signal and the second level output signal.
Claim 3
Dependent Claim
30 words
The logic circuit of claim 1, wherein the first output transistor circuit means comprises a first bipolar transistor, and the second output transistor circuit means comprises a second bipolar transistor.
Claim 4
Dependent Claim
24 words
The logic circuit of claim 2, further comprising; means for discharging the charge of the second bipolar transistor in response to the input signal.
Claim 5
Dependent Claim
32 words
The logic circuit of claim 3, wherein the current control means also includes a Schottky diode connected to the second MOS transistor for limiting current flow to the second MOS transistor means.
Claim 6
Dependent Claim
54 words
The logic circuit of claim 1, also including first and second power source terminals; and first and second input terminals for receiving the input signal; and wherein the output control means includes third and fourth MOS transistors each having a gate electrode connected to a corresponding one of the first and second input terminals.
Claim 7
Dependent Claim
75 words
The logic circuit of claim 5, wherein the output circuit means includes first and second nodes, the third and fourth MOS transistors being in parallel between the first and second nodes, and the second MOS transistor means includes fifth and sixth MOS transistors each having a gate electrode connected to a corresponding one of the first and second input terminals, and being connected in series between the first MOS transistor means and the second node.
Claim 8
Dependent Claim
63 words
The logic circuit of claim 5, wherein the output circuit means includes first and second nodes, the third and fourth MOS transistor s being in series between the first and second nodes, and the second MOS transistors each having a gate electrode connected to a corresponding input terminals, and being connected in parallel between the first MOS transistor means and the second node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |