Wiring structures for semiconductor memory device

Claim 2

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; corresponding portions of each bit line of each bit line pair alternating laterally and being located in different planes parallel to the surface of said substrate; the total length of said each bit line located in any one of said different planes parallel to the surface of said substrate being equal to the total length of the other bit line of said bit line pair located in the same plane of said substrate.

Claim 3

A semiconductor memory in accordance with claim 1, wherein contact holes are formed in the vicinity of the region where said corresponding portions of the bit lines alternate.

Claim 4

A semiconductor memory in accordance with claim 1, wherein said memory comprises a dynamic memory device.

Claim 5

A semiconductor memory in accordance with claim 1, wherein said memory comprises a static memory device.

Claim 6

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; each bit line pair including successive sections of parallel bit line portions located in a first plame, parallel to displaced from said major surface of said substrate; said successive sections comprising bit line portions interchanged with corresponding portions alternately and laterally on said substrate along the length of said bit line pair, each bit line pair having at least one intersecting portion for interconnecting said successive sections; and said at least one intersecting portion of said bit line pair being located in a second plane of said substrate different from said first plane, wherein each bit line of each bit line pair includes at least one said intersecting portion located in said second plane.

Claim 7

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; each bit line pair including successive sections of parallel bit line portions located in a first plame, parallel to displaced from said major surface of said substrate; said successive sections comprising bit line portions interchanged with corresponding portions alternately and laterally on said substrate along the length of said bit line pair, each bit line pair having at least one intersecting portion for interconnecting said successive sections; and said at least one intersecting portion of said bit line pair being located in a second plane of said substrate different from said first plane, wherein each bit line of each bit line pair includes at least one said intersecting portion located in said second plane.

Claim 8

A semiconductor memory in accordance with claim 5, wherein said at least one intersecting portion of said bit line pair comprises an impurity region.

Claim 9

A semiconductor memory in accordance with claim 5, wherein said at least one intersecting portion of said bit line pair comprises an additional conductive layer.

Claim 10

A semiconductor memory in accordance with claim 7, wherein said additional conductive layer comprises a conductive layer in a lower plane.

Claim 11

A semiconductor memory in accordance with claim 7, wherein said additional conductive layer comprises a conductive layer in a higher plane.

Claim 12

A semiconductor memory in accordance with claim 5, wherein each bit line pair has said at least one intersecting portion in the region where said memory cells are formed.

Claim 13

A semiconductor memory in accordance with claim 5, wherein each bit line pair has said at least one intersecting portion in the region other than the region where said memory cells are formed.

Claim 14

A semiconductor memory in accordance with claim 5, wherein said memory comprises a dynamic memory device.

Claim 15

A semiconductor memory in accordance with claim 5, wherein said memory comprises a static memory device.

Claim 16

In a semiconductor memory of a type having semiconductor substrate, word lines and bit lines intersecting each other on a major surface of said substrate and memory cells arranged at intersections of said word lines and said bit lines, said bit lines arranged in the form of parallel bit line pairs, and sense amplifier means for sensing voltage differentials of said bit line pairs, and wherein signals capacitively coupled to said bit line pairs tend to induce error voltage differentials therein, a method of reducing coupling of voltage differentials to a bit line pair, comprising the steps of: locating successive sections of parallel bit line portions said bit lines of each bit line pair in a first plane, parallel to and displaced from said major surface of said substrate; interchanging locations of corresponding parallel portions of said sections of the bit lines of each bit line pair alternately and laterally on said substrate along the length of said bit line pair; interconnecting said successive sections by intersecting bit line portions; locating at least one intersecting portion of said bit line pair in a second plane of said substrate different from said first plane, each bit line of each bit line pair including at least one said intersecting portion located in said second plane.

Claim 17

In a semiconductor memory of a type having semiconductor substrate, word lines and bit lines intersecting each other on a major surface of said substrate and memory cells arranged at intersections of said word lines and said bit lines, said bit lines arranged in the form of parallel bit line pairs, and sense amplifier means for sensing voltage differentials of said bit line pairs, and wherein signals capacitively coupled to said bit line pairs tend to induce error voltage differentials therein, a method of reducing coupling of voltage differentials to a bit line pair, comprising the steps of: locating successive sections of parallel bit line portions said bit lines of each bit line pair in a first plane, parallel to and displaced from said major surface of said substrate; interchanging locations of corresponding parallel portions of said sections of the bit lines of each bit line pair alternately and laterally on said substrate along the length of said bit line pair; interconnecting said successive sections by intersecting bit line portions; locating at least one intersecting portion of said bit line pair in a second plane of said substrate different from said first plane, each bit line of each bit line pair including at least one said intersecting portion located in said second plane.

Claim 18

In a semiconductor memory of a type having semiconductor substrate, word lines and bit lines intersecting each other on a major surface of said substrate and memory cells arranged at intersections of said word lines and said bit lines, said bit lines arranged in the form of parallel bit line pairs, and sense amplifier means for sensing voltage differentials of said bit line pairs, and wherein signals capacitively coupled to said bit line pairs tend to induce error voltage differentials therein, a method of reducing coupling of voltage differentials to a bit line pair, comprising the steps of: interchanging locations of corresponding sections of the bit lines of each bit line pair alternately and laterally on said substrate along the length of said bit line pair; and interchanging locations of said corresponding sections of each of said bit lines of said bit line pair vertically between first and second planes, parallel to and displaced from said major surface of said substrate, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.

Claim 19

In a semiconductor memory of a type having semiconductor substrate, word lines and bit lines intersecting each other on a major surface of said substrate and memory cells arranged at intersections of said word lines and said bit lines, said bit lines arranged in the form of parallel bit line pairs, and sense amplifier means for sensing voltage differentials of said bit line pairs, and wherein signals capacitively coupled to said bit line pairs tend to induce error voltage differentials therein, a method of reducing coupling of voltage differentials to a bit line pair, comprising the steps of: interchanging locations of corresponding sections of the bit lines of each bit line pair alternately and laterally on said substrate along the length of said bit line pair; and interchanging locations of said corresponding sections of each of said bit lines of said bit line pair vertically between first and second planes, parallel to and displaced from said major surface of said substrate, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.

Claim 20

A method in accordance with claim 15, including the step of aligning facing sides of said bit lines of each said bit line pair on a common plane normal to said substrate.

Claim 21

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, each bit line comprising a plurality of different portions arranged in first and second parallel planes of said substrate, said bit lines arranged in the form of bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; the bit lines of at least one bit pair forming a twisted pair by intersecting each other at an even number of crossover regions of said substrate; the bit lines of at least one bit line pair in said crossover regions lying respectively in said first and said second planes and being parallel to each other in portions of said substrate outside said crossover regions, wherein within the crossover regions of said twisted pair the composite length of said bit line lying in said first plane of said substrate is equal to the composite length of the same bit line lying in said second plane of said substrate.

Claim 22

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, each bit line comprising a plurality of different portions arranged in first and second parallel planes of said substrate, said bit lines arranged in the form of bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; the bit lines of at least one bit pair forming a twisted pair by intersecting each other at an even number of crossover regions of said substrate; the bit lines of at least one bit line pair in said crossover regions lying respectively in said first and said second planes and being parallel to each other in portions of said substrate outside said crossover regions, wherein within the crossover regions of said twisted pair the composite length of said bit line lying in said first plane of said substrate is equal to the composite length of the same bit line lying in said second plane of said substrate.

Claim 23

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; the bit lines of successive portions of each bit line pair alternating laterally and being parallel to a plane of said substrate and lying alternately at first and second planes parallel to the surface of said substrate to form a twisted pair, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.

Claim 24

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; the bit lines of successive portions of each bit line pair alternating laterally and being parallel to a plane of said substrate and lying alternately at first and second planes parallel to the surface of said substrate to form a twisted pair, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.

Claim 25

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, each bit line comprising a plurality of different portions arranged in first and second parallel planes of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; each bit line pair divided to form successive alternate parallel and crossover portions, the bit lines being parallel to each other in the parallel portions, the bit lines in said crossover portions being located in different planes parallel to the major surface of the substrate and intersecting with each other so that the bit lines in adjacent parallel portions are interchanged, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.

Claim 26

A semiconductor memory comprising: a semiconductor substrate having a major surface; word lines and bit lines intersecting each other on the major surface of said substrate, each bit line comprising a plurality of different portions arranged in first and second parallel planes of said substrate, said bit lines arranged in the form of parallel bit line pairs; memory cells arranged at intersections of said word lines and said bit lines; and sense amplifier means for sensing voltage differentials of each bit line pair; each bit line pair divided to form successive alternate parallel and crossover portions, the bit lines being parallel to each other in the parallel portions, the bit lines in said crossover portions being located in different planes parallel to the major surface of the substrate and intersecting with each other so that the bit lines in adjacent parallel portions are interchanged, each bit line being of substantially the same length in each plane as the length of the corresponding bit line of the bit line pair.