Semiconductor integrated circuit device constructed by polycell technique

Claim 2

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a first insulating layer formed on said semiconductor substrate; a polysilicon wiring layer formed on said first insulating layer, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays and connected at one end to one of the input terminals of the corresponding unit cell; a second insulating layer formed on said first insulating layer and said polysilicon wiring layers; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above said polysilicon wiring layer, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said polysilicon wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said polysilicon wiring layer.

Claim 3

A device according to claim 1, wherein said first and second metal wiring layers comprise aluminum layers formed by using the polycell technique, respectively.

Claim 4

A device according to claim 1, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 5

A device according to claim 1, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.

Claim 6

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a first insulating layer formed on said semiconductor substrate; a polysilicon wiring layer formed on said first insulating layer embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends and a portion broader than the other portions, one of said ends being connected to one of the input terminals of the corresponding unit cell; a second insulating layer formed on said first insulating layer and said polysilicon wiring layers; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above the broader portion of said polysilicon wiring layer, for connecting said first metal wiring layer to said second metal wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said polysilicon wiring layer.

Claim 7

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a first insulating layer formed on said semiconductor substrate; a polysilicon wiring layer formed on said first insulating layer embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends and a portion broader than the other portions, one of said ends being connected to one of the input terminals of the corresponding unit cell; a second insulating layer formed on said first insulating layer and said polysilicon wiring layers; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above the broader portion of said polysilicon wiring layer, for connecting said first metal wiring layer to said second metal wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said polysilicon wiring layer.

Claim 8

A device according to claim 5, wherein said first and second metal wiring layers comprise aluminum layers formed by using the polycell technique, respectively.

Claim 9

A device according to claim 5, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 10

A device according to claim 5, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.

Claim 11

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a first insulating layer formed on said semiconductor substrate; a polysilicon wiring layer formed on said first insulating layer, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in the wiring region, and having a portion broader than the other portions; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in the wiring region, extending at right angles to said first metal wiring layer, and having a portion broader than the other portions, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and above said polysilicon wiring layer in a position corresponding to the broader portions of said first and second metal wiring layers, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said polysilicon wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said polysilicon wiring layer.

Claim 12

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a first insulating layer formed on said semiconductor substrate; a polysilicon wiring layer formed on said first insulating layer, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in the wiring region, and having a portion broader than the other portions; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in the wiring region, extending at right angles to said first metal wiring layer, and having a portion broader than the other portions, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and above said polysilicon wiring layer in a position corresponding to the broader portions of said first and second metal wiring layers, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said polysilicon wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said polysilicon wiring layer.

Claim 13

A device according to claim 9, wherein said first and second metal wiring layers comprise aluminum layers formed by the polycell technique.

Claim 14

A device according to claim 9, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 15

A device according to claim 9, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.

Claim 16

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays and connected at one end to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above said diffusion wiring layer, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said diffusion wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 17

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays and connected at one end to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above said diffusion wiring layer, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said diffusion wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 18

A device according to claim 13, wherein said first and second metal wiring layers comprise aluminum layers formed by the polycell technique.

Claim 19

A device according to claim 13, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 20

A device according to claim 13, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.

Claim 21

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring regiuon, extending at right angles to said cell arrays, and having two ends and a portion broader than the other portions, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above the broader portion of said diffusion wiring layer, for connecting said first metal wiring layer to said second metal wiring layer; and a contact hole firmed in said second insulating layers, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 22

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring regiuon, extending at right angles to said cell arrays, and having two ends and a portion broader than the other portions, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in said wiring region; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in said wiring region, and extending at right angles to said first metal wiring layer, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and positioned above the broader portion of said diffusion wiring layer, for connecting said first metal wiring layer to said second metal wiring layer; and a contact hole firmed in said second insulating layers, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 23

A device according to claim 17, wherein said first and second metal wiring layers comprise aluminum layers formed by using the polycell technique, respectively.

Claim 24

A device according to claim 17, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 25

A device according to claim 17, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.

Claim 26

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in the wiring region, and having a portion broader than the other portions; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in the wiring region, extending at right angles to said first metal wiring layer, and having a portion broader than the other portions, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and above said diffusion wiring layer in a position corresponding to the broader portions of said first and second metal wiring layers, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said diffusion wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 27

A semiconductor IC device made by the polycell technique, comprising: a semiconductor substrate; various functional circuits formed in one major surface of said semiconductor substrate; a plurality of cell arrays each constituted by unit cells having said functional circuits; a wiring region formed between any two adjacent cell arrays; a diffusion wiring layer formed in one major surface region of said semiconductor substrate, embedded in the corresponding unit cell, positioned in said wiring region, extending at right angles to said cell arrays, and having two ends, one of said ends being connected to one of the input terminals of the corresponding unit cell; a first insulating layer formed on said semiconductor substrate, that portion of said first insulating layer which contacts said diffusion wiring layer is thinner than the other portions; a second insulating layer formed on said first insulating layer; a first metal wiring layer formed on that portion of said second insulating layer which is positioned in the wiring region, and having a portion broader than the other portions; a third insulating layer formed on said first metal wiring layer and said second insulating layer; a second metal wiring layer formed on that portion of said third insulating layer which is positioned in the wiring region, extending at right angles to said first metal wiring layer, and having a portion broader than the other portions, part of said second metal wiring layer being selectively connected to one of the output terminals of said unit cell; a via contact hole formed in said third insulating layer and above said diffusion wiring layer in a position corresponding to the broader portions of said first and second metal wiring layers, for connecting said second metal wiring layer to said first metal wiring layer, said via contact hole having an axis aligned with that of said diffusion wiring layer; and a contact hole formed in said second insulating layer, for connecting said first metal wiring layer to said diffusion wiring layer.

Claim 28

A device according to claim 21, wherein said first and second metal wiring layers comprise aluminum layers formed by the polycell technique.

Claim 29

A device according to claim 21, wherein said first metal wiring layer is formed parallel to said cell arrays, and said second metal wiring layer is formed perpendicular to said cell arrays.

Claim 30

A device according to claim 21, wherein said first metal wiring layer is formed perpendicular to said cell arrays, and said second metal wiring layer is formed parallel with said cell arrays.