Multi-level interconnection system

Abstract

Abstract 1433624 Integrated circuit metallization INTERNATIONAL BUSINESS MACHINES CORP 21 Sept 1973 [27 Oct 1972] 44320/73 Heading H1K A method of forming a multilevel interconnection system for an integrated circuit comprises forming a patterned metallic layer 34 on an insulating layer 32 on a semi-conductor body 10, e.g. Si, depositing a second insulating layer 36 over the said insulating and metallic layers, the second insulating layer 36 being etchable by an etchant to which the insulating layer 32 is relatively inert, etching a hole through layer 36, using said etchant, over a desired portion of layer 34, and depositing a second metal layer 42 on layer 36 so as to contact the exposed portion of layer 34, the minimum width of the hole being # the maximum width of the underlying portion of layer 34. Layer 42 is subsequently patterned by photo-etching. Layers 32 and 36 may be of Si 3 N 4 and SiO 2 respectively (when buffered HF may be used as etchant), or vice versa; Al 2 O 3 and SiO 2 ; or thermally grown SiO 2 and SiO 2 pyrolytically deposited at between 400 and 550‹ C. The metallic layers may be of the same or different materials, or laminates or alloys, including Al, Cr, Cu, Si, Ag, and Ta; when layer 42 is of Al or Al alloy, an etchant is used which does not affect layer 34, which may be of Cr-Ag-Cr or Cr-Cu-Cr, e.g. a solution of H 2 O 2 and NH 4 F. Additional insulating layers 30 and 44 may also be present on the device. Further metallic layers may be added in a similar process.

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