Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region, having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second integrated circuit region; and a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals also formed on said single semiconductor substrate outside of said first and second integrated circuit regions.

Claim 3

A device according to claim 1, wherein said first integrated circuit region comprises a central processing unit, and said second integrated circuit region comprises a memory or other peripheral circuit.

Claim 4

A device according to claim 1, wherein each of said first and second circuit regions comprises complementary metal oxide semiconductors.

Claim 5

A device according to claim 1, further including a first wiring layer and a second wiring layer, wherein a region of said second wiring layer connects said outer bonding pads to said external terminals and is located between said first and second integrated circuit regions.

Claim 6

A device according to claim 4, wherein said external terminals are formed co-planar with said first wiring layer, and said outer bonding pads are formed on an insulating interlayer which is formed on said first wiring layer.

Claim 7

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; and a plurality of outer bonding pads formed on a region of said semiconductor substrate which is located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of a said semiconductor integrated circuit device.

Claim 8

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; and a plurality of outer bonding pads formed on a region of said semiconductor substrate which is located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of a said semiconductor integrated circuit device.

Claim 9

A device according to claim 6, wherein said first integrated circuit region comprises a central processing unit, and said second integrated circuit region comprises a memory or other peripheral circuit.

Claim 10

A device according to claim 6, wherein each of said first and second circuit regions comprises complementary metal oxide semiconductors.

Claim 11

A device according to claim 6, further including a first wiring layer and a second wiring layer, wherein a region of said second wiring layer connects said outer bonding pads and is located between said first and second integrated circuit regions.

Claim 12

A device according to claim 9 wherein said external terminals are formed co-planar with said first wiring layer, and said outer bonding pads are formed on an insulating interlayer which is formed on said first wiring layer.

Claim 13

A semiconductor integrated circuit device comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second integrated circuit region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals also formed on said single semiconductor substrate outside of said integrated circuit regions; a first wiring layer formed on each of said first and second integrated circuit regions; and a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions.

Claim 14

A semiconductor integrated circuit device comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second integrated circuit region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals also formed on said single semiconductor substrate outside of said integrated circuit regions; a first wiring layer formed on each of said first and second integrated circuit regions; and a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions.

Claim 15

A device according to claim 11, wherein said first integrated circuit region comprises a central processing unit, and said second integrated circuit region comprises a memory or other peripheral circuit.

Claim 16

A device according to claim 11, wherein each of said first and second circuit regions comprise complementary metal oxide semiconductors.

Claim 17

A device according to claim 11, wherein the region of said second wiring layer which connects said external lead contacts is located between said first and second integrated circuit regions.

Claim 18

A device according to claim 11, wherein said external terminals are formed co-planar with said first wiring layer, and said outer bonding pads are formed on an insulating interlayer which is formed on said first wiring layer.

Claim 19

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, said function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on said semiconductor substrate located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said resultant semiconductor integrated circuit device; a first wiring layer formed on each of said first and second integrated circuit regions; and a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit region and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions.

Claim 20

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, said function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on said semiconductor substrate located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said resultant semiconductor integrated circuit device; a first wiring layer formed on each of said first and second integrated circuit regions; and a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit region and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions.

Claim 21

A device according to claim 16, wherein said first integrated circuit region comprises a central processing unit, and said second integrated circuit region comprises a memory or other peripheral circuit.

Claim 22

A device according to claim 16, wherein each of said first and second circuit regions comprise complementary metal oxide semiconductors.

Claim 23

A device according to claim 16, wherein the region of said second wiring layer which connects said external lead contacts is located between said first and second integrated circuit regions.

Claim 24

A device according to claim 16, wherein said external terminals are formed co-planar with said first wiring layer, and said outer bonding pads are formed on an insulating interlayer which is formed on said first wiring layer.

Claim 27

A method according to claim 21, further comprising the steps of forming an insulating film on said integrated circuit regions, and forming said second wiring layer on said insulating film.

Claim 28

A method according to claim 22, further comprising the step of forming said outer bonding pads on said insulating film simultaneously with the formation of said second wiring layer.

Claim 29

A semiconductor integrated circuit device, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region, having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second semiconductor region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals, said bonding pads also formed on said single semiconductor substrate outside of said first and second integrated circuit regions; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit and from that of said second integrated circuit.

Claim 30

A semiconductor integrated circuit device, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region, having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second semiconductor region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals, said bonding pads also formed on said single semiconductor substrate outside of said first and second integrated circuit regions; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit and from that of said second integrated circuit.

Claim 31

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on a region of said semiconductor substrate which is located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said semiconductor integrated circuit device; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit and from that of said second integrated circuit.

Claim 32

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on a region of said semiconductor substrate which is located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said semiconductor integrated circuit device; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit and from that of said second integrated circuit.

Claim 33

A semiconductor integrated circuit device, comprising: a single semiconductor substrate; a first integrated circuit region, formed on said single semiconductor substrate, having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region, having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second semiconductor region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals also formed on said single semiconductor substrate outside of said integrated circuit regions; a first wiring layer formed on each of said first and second integrated circuit regions; a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions; and said first and second integrated circuit regions electrically connected to form said semiconductor integrated circuit device having functions different from those of said second integrated circuit region.

Claim 34

A semiconductor integrated circuit device, comprising: a single semiconductor substrate; a first integrated circuit region, formed on said single semiconductor substrate, having external terminals located at a periphery of said first integrated circuit region; a second integrated circuit region, having a different circuit function from said first integrated circuit region, also formed on said single semiconductor substrate and also having external terminals located at a periphery of said second semiconductor region; a plurality of outer bonding pads for connection to said first and second integrated circuit region external terminals also formed on said single semiconductor substrate outside of said integrated circuit regions; a first wiring layer formed on each of said first and second integrated circuit regions; a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions; and said first and second integrated circuit regions electrically connected to form said semiconductor integrated circuit device having functions different from those of said second integrated circuit region.

Claim 35

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on said semiconductor substrate, located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said semiconductor integrated circuit device; a first wiring layer formed on each of said first and second integrated circuit regions; a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit region and that of said second integrated circuit region.

Claim 36

A semiconductor integrated circuit device for providing the functions of two or more discrete integrated circuit chips, each of which have original bonding pads, comprising: a single semiconductor substrate; a first integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said first integrated circuit chip, and having external terminals corresponding to said original bonding pads of said first integrated circuit chip; a second integrated circuit region formed on said single semiconductor substrate, having substantially the same pattern and function as said second integrated circuit chip, and having external terminals corresponding to said original bonding pads of said second integrated circuit chip, the function of said second integrated circuit region being different from that of said first integrated circuit region; a plurality of outer bonding pads formed on said semiconductor substrate, located outside said integrated circuit regions, said plurality of outer bonding pads being used as bonding pads of said semiconductor integrated circuit device; a first wiring layer formed on each of said first and second integrated circuit regions; a second wiring layer connecting one of said external terminals of said first integrated circuit region and one of said external terminals of said second integrated circuit region and also connecting one of said external terminals of said first or second integrated circuit regions and one of said outer bonding pads, said second wiring layer being formed on an insulating interlayer deposited on said first wiring layer in each of said first and second integrated circuit regions; and said first and second integrated circuit regions being electrically connected to form said semiconductor integrated circuit device having a function different from that of said first integrated circuit region and that of said second integrated circuit region.