EP0167281A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-05-31
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Granted: —
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Expires: 2005-05-31
Abstract
Abstract A semiconductor memory device including a plurality of bit line pairs (BLOa, BLOa to BL3a, BL3a; BLOb, BLOb to BL3b, BL3b; BLOc, BLOc to BL3c, BL3c) and a plurality of sense amplifiers (SAO, to SA3) each for amplifying the voltage difference between two bit lines of a bit line pair. The two bit lines of every other bit line pair are made to intersect at central portions (CP) of the two bit lines, whereby the noise between adjacent bit lines is reduced and read errors are prevented.
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 16:04
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/002; H01G4/018; H01G4/06; H01G4/08; H01G4/12; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C5/00; G11C5/02; G11C5/025; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
95 words
A semiconductor memory device comprising: a plurality of bit line pairs, each comprised of two adjacently arranged bit lines and a plurality of sense amplifiers, each connected to one of said bit line pairs, each of said sense amplifiers amplifying the voltage difference between the two bit lines of the corresponding bit line pair to which said each of said sense amplifiers is connected; the two bit lines of at least every other bit line pair of said bit line pairs being made to intersect at at least one portion of said two bit lines.
Claim 2
Dependent Claim
95 words
A semiconductor memory device comprising: a plurality of bit line pairs, each comprised of two adjacently arranged bit lines and a plurality of sense amplifiers, each connected to one of said bit line pairs, each of said sense amplifiers amplifying the voltage difference between the two bit lines of the corresponding bit line pair to which said each of said sense amplifiers is connected; the two bit lines of at least every other bit line pair of said bit line pairs being made to intersect at at least one portion of said two bit lines.
Claim 3
Dependent Claim
39 words
A semiconductor memory device as set forth in claim 1, wherein the two bit lines of every other bit line pair of said bit line pairs are made to intersect at only one portion of said two bit lines.
Claim 4
Dependent Claim
28 words
A semiconductor memory device as set forth in claim 1 or 2 wherein said bit line pairs extend in parallel with each other except for said intersection portions.
Claim 5
Dependent Claim
29 words
A semiconductor memory device as set forth in claim 1, 2 or 3 wherein said portions are central portions in the direction in which said bit line pairs extend.
Claim 6
Dependent Claim
79 words
A semiconductor memory device as set forth in claim 1, 2, 3 or 4, further comprising a plurality of word lines and a plurality of one-transistor one-capacitor type memory cells each connected between one of said bit lines and one of said word lines, and, in each of said bit line pairs, said memory cells are connected between each one of said word lines and either one of the two bit lines of said each said bit line pair.
Claim 7
Dependent Claim
57 words
A semiconductor memory device as set forth in any preceding claim, wherein the two bit lines of every other bit line pair are made to intersect at central portions in the direction in which said bit line pairs extend and the two bit lines of the remaining bit line pairs are made to intersect at other portions.
Claim 8
Dependent Claim
28 words
A semiconductor memory device as set forth in claim 6, wherein said other portions are both in a top and a bottom half of said bit line pairs.
Claim 9
Dependent Claim
30 words
A semiconductor memory device as set forth in claim 7, wherein the two bit lines of said remaining bit line pairs are also made to intersect at said central portions.
References Cited (Backward Citations)
No citation records indexed.
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