Large-scale EPROM memory with a high coupling factor

Claim 1

A memory array comprising plural floating gate transistors each including a source, drain, control gate and floating gate; word lines (LM1, LM2) extending along a first direction, called row direction, interconnecting the control gates (25) of the floating gate transistors; bit lines (LB1, LB2) extending along a second direction, called column direction, interconnecting the drains of the floating gate transistors; a constant-potential line (B) extending along a column and formed by diffusion of a first conductivity type interconnecting the sources of the floating gate transistors, the constant-potential line being arranged between each pair of bit lines, all the constant-potential lines being at the same potential; an isolation area (24) extending along a column arranged on a side of each bit line opposite to one of the constant-potential lines; a conductive pad (E) covering longitudinal sides of the isolation areas (24), said pad (E) being made of the same material as the material forming the floating gates (23) of the floating gate transistors; a conductive area (35) connecting the floating gate (23) of each transistor to the corresponding pad, the conductive area being superposed with the corresponding word line from which it is separated by an isolation layer (28).