Patent US6338445B1 successfully refreshed from Google Patents.
US5010259A
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US
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Voltage boosting circuit and operating method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1989-12-21
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Granted: 1991-04-23
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Expires: 2009-12-21
Abstract
Abstract An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.
Inventors
- 👤 Yoshinori Inoue
- 👤 Masaki Kumanoya
- 👤 Takahiro Komatsu
- 👤 Yasuhiro Konishi
- 👤 Katsumi Dosaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:41
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
175 words
A voltage boosting circuit provided in a semiconductor integrated circuit device for generating at an output terminal an output signal boosted to be higher than a supply voltage, comprising: charging means provided between a power supply and a prescribed node in said voltage boosting circuit for being conductive when the potential of said node is lower than a given value, thereby charging said prescribed node, and being nonconductive when the potential of said prescribed node is higher than a given value, thereby preventing charge from flowing back to the power supply from said prescribed node, signal inverting means responsive to an input signal for providing said output signal inverted from said input signal to an output terminal thereof based on the potential of said prescribed node and a ground potential, delay means coupled between said output terminal and said prescribed node for delaying said output signal by a given time, and capacitor means responsive to the output of said delay means for boosting the potential of said prescribed node and consequently boosting said output signal.
Claim 2
Dependent Claim
175 words
A voltage boosting circuit provided in a semiconductor integrated circuit device for generating at an output terminal an output signal boosted to be higher than a supply voltage, comprising: charging means provided between a power supply and a prescribed node in said voltage boosting circuit for being conductive when the potential of said node is lower than a given value, thereby charging said prescribed node, and being nonconductive when the potential of said prescribed node is higher than a given value, thereby preventing charge from flowing back to the power supply from said prescribed node, signal inverting means responsive to an input signal for providing said output signal inverted from said input signal to an output terminal thereof based on the potential of said prescribed node and a ground potential, delay means coupled between said output terminal and said prescribed node for delaying said output signal by a given time, and capacitor means responsive to the output of said delay means for boosting the potential of said prescribed node and consequently boosting said output signal.
Claim 3
Dependent Claim
36 words
A voltage boosting circuit according to claim 1, wherein said charging means comprises an N channel MOS field-effect transistor provided between the power supply and said prescribed node with its gate connected to the power supply.
Claim 4
Dependent Claim
30 words
A voltage boosting circuit according to claim 1, wherein said charging means comprises a diode having its anode connected to the power supply and its cathode to said prescribed node.
Claim 5
Dependent Claim
62 words
A voltage boosting circuit according to claim 1, wherein said signal inverting means comprises a P channel MOS field-effect transistor provided between said prescribed node and said output terminal for receiving said input signal at the gate thereof, and an N channel MOS field-effect transistor provided between said output terminal and the ground for receiving said input signal at the gate thereof.
Claim 6
Dependent Claim
27 words
A voltage boosting circuit according to claim 4, wherein said P channel MOS field-effect transistor has its source and substrate connected in common to said prescribed node.
Claim 7
Dependent Claim
20 words
A voltage boosting circuit according to claim 1, wherein said delay means comprises a plurality of inverters connected in series.
Claim 8
Dependent Claim
19 words
A voltage boosting circuit according to claim 1, wherein said semiconductor integrated circuit device comprises a semiconductor memory unit.
Claim 9
Dependent Claim
19 words
A voltage boosting circuit according to claim 7, wherein said semiconductor memory unit comprises a dynamic random access memory.
Claim 10
Dependent Claim
111 words
A voltage boosting circuit provided in a semiconductor integrated circuit for receiving an input signal and generating an output signal boosted to a value higher than that of a source of supply voltage, comprising: means coupled to said supply voltage source for charging a node; signal inverter means coupled to said node for generating on an output line an output signal inverted from said input signal; and feedback circuit means for feeding back said output signal as a feedback signal, said feedback circuit means including (a) delay means for delaying said output signal, and (b) coupling means responsive to said delay means for capacitively coupling said feedback signal to said node.
Claim 11
Dependent Claim
111 words
A voltage boosting circuit provided in a semiconductor integrated circuit for receiving an input signal and generating an output signal boosted to a value higher than that of a source of supply voltage, comprising: means coupled to said supply voltage source for charging a node; signal inverter means coupled to said node for generating on an output line an output signal inverted from said input signal; and feedback circuit means for feeding back said output signal as a feedback signal, said feedback circuit means including (a) delay means for delaying said output signal, and (b) coupling means responsive to said delay means for capacitively coupling said feedback signal to said node.
Claim 12
Dependent Claim
43 words
The circuit of claim 9, wherein said charging means includes unidirectional conducting means for preventing flow of current to the supply voltage source when the output voltage has a magnitude that is boosted to be greater than that of said supply voltage source.
Claim 13
Independent Claim
113 words
A method of generating a boosted voltage that is higher than a supply voltage provided by a supply voltage source, comprising the steps of: receiving a binary input signal having a value that changes successively between logic high and logic low voltage levels; inverting said binary input signal to provide an output signal; from said supply voltage source, charging a node in response to the input signal and in accordance with a charge previously stored on said node; obtaining a feedback signal derived from said output signal; delaying said feedback signal by a predetermined delay time to provide a delayed feedback signal; and capacitively coupling said delayed feedback signal to boost said node.
Claim 14
Independent Claim
113 words
A method of generating a boosted voltage that is higher than a supply voltage provided by a supply voltage source, comprising the steps of: receiving a binary input signal having a value that changes successively between logic high and logic low voltage levels; inverting said binary input signal to provide an output signal; from said supply voltage source, charging a node in response to the input signal and in accordance with a charge previously stored on said node; obtaining a feedback signal derived from said output signal; delaying said feedback signal by a predetermined delay time to provide a delayed feedback signal; and capacitively coupling said delayed feedback signal to boost said node.
Claim 15
Dependent Claim
167 words
A voltage boosting circuit provided in a semiconductor integrated circuit device for generating at an output terminal an output signal boosted to be higher than a supply voltage, comprising: an inverter circuit comprising at least first and second transistors in series for inverting an input signal to produce said output signal; a charging circuit comprising a transistor connected to said source of said supply voltage and in series with said inverter circuit, a node being established between said inverter circuit and said charging circuit, and a feedback circuit for feeding said output signal to said node, said feedback circuit comprising, in series, (a) a capacitor, and (b) an even number of inverter circuits forming a delay, said charging circuit being conductive when the potential of said node is lower than a given value, thereby charging said prescribed node, and being non-conductive when the potential of said node is higher than said given value, thereby preventing charge from flowing back to said source supply voltage from said node.
Claim 16
Dependent Claim
167 words
A voltage boosting circuit provided in a semiconductor integrated circuit device for generating at an output terminal an output signal boosted to be higher than a supply voltage, comprising: an inverter circuit comprising at least first and second transistors in series for inverting an input signal to produce said output signal; a charging circuit comprising a transistor connected to said source of said supply voltage and in series with said inverter circuit, a node being established between said inverter circuit and said charging circuit, and a feedback circuit for feeding said output signal to said node, said feedback circuit comprising, in series, (a) a capacitor, and (b) an even number of inverter circuits forming a delay, said charging circuit being conductive when the potential of said node is lower than a given value, thereby charging said prescribed node, and being non-conductive when the potential of said node is higher than said given value, thereby preventing charge from flowing back to said source supply voltage from said node.
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