US4746824A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High potential hold circuit
Assignee: Toshiba Corp
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Filing: 1986-10-21
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Granted: 1988-05-24
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Expires: 2006-10-21
Abstract
Abstract This invention provides a high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node; a discharge enhancement mode MOS transistor for discharging the potential of the high potential node, having one end connected to the ground potential, the other end connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between the high potential node and the high potential hold transistor; and charge-discharge means for charging and discharging a potential of a gate of the field relaxation transistor.
Inventors
- 👤 Koichi Magome
- 👤 Hiroyuki Koinuma
- 👤 Haruki Toda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; G; G11; G11C; G11C5/00; G11C5/14; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
159 words
A high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in a non-conducting state after the node is charged, having one terminal connected to a first input signal and a second terminal connected to the high potential node; an enhancement mode MOS transistor for discharging the potential of the high potential node, having one terminal connected to the ground potential, a second terminal connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between a high potential node and a high potential hold transistor; and means for charging and discharging a potential of a gate of the field relaxation transistor having a depletion mode MOS transistor located between the gate of the field relaxation enhancement mode MOS transistor and a power supply.
Claim 2
Dependent Claim
159 words
A high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in a non-conducting state after the node is charged, having one terminal connected to a first input signal and a second terminal connected to the high potential node; an enhancement mode MOS transistor for discharging the potential of the high potential node, having one terminal connected to the ground potential, a second terminal connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between a high potential node and a high potential hold transistor; and means for charging and discharging a potential of a gate of the field relaxation transistor having a depletion mode MOS transistor located between the gate of the field relaxation enhancement mode MOS transistor and a power supply.
Claim 3
Dependent Claim
30 words
A high potential hold circuit according to claim 1 wherein the field relaxation transistor is located between the enhancement mode MOS transistor for discharging and the high potential hold transistor.
Claim 4
Dependent Claim
24 words
A high potential hold circuit according to claim 2 wherein the depletion mode MOS transistor has a gate connected to the first input signal.
Claim 5
Dependent Claim
24 words
A high potential hold circuit according to claim 2 wherein the depletion mode MOS transistor has a gate connected to the high potential node.
Claim 6
Dependent Claim
29 words
A high potential hold circuit according to claim 2 wherein the depletion mode MOS transistor has a gate connected to a second terminal of the high potential hold transistor.
Claim 7
Dependent Claim
45 words
A high potential hold circuit according to claim 3 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 8
Dependent Claim
45 words
A high potential hold circuit according to claim 4 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 9
Dependent Claim
45 words
A high potential hold circuit according to claim 5 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 10
Dependent Claim
35 words
A high potential hold circuit according to claim 1 wherein the field relaxation transistor is located between the high potential node and a junction node of the high potential hold transistor and the discharge transistor.
Claim 11
Dependent Claim
24 words
A high potential hold circuit according to claim 9 wherein the depletion mode MOS transistor has a gate connected to the first input signal.
Claim 12
Dependent Claim
24 words
A high potential hold circuit according to claim 9 wherein the depletion mode MOS transistor has a gate connected to the high potential node.
Claim 13
Dependent Claim
29 words
A high potential hold circuit according to claim 9 wherein the depletion mode MOS transistor has a gate connected to a second terminal of the high potential hold transistor.
Claim 14
Dependent Claim
45 words
A high potential hold circuit according to claim 10 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 15
Dependent Claim
45 words
A high potential hold circuit according to claim 11 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 16
Dependent Claim
45 words
A high potential hold circuit according to claim 12 wherein the means for charging and discharging also includes a first enhancement mode MOS transistor located between the gate of the field relaxation transistor and the power supply, having a gate connected to the power supply.
Claim 17
Dependent Claim
161 words
A high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in a non-conducting state after the node is charged, having one terminal connected to a first input signal and a second terminal connected to the high potential node; an enhancement mode MOS transistor for discharging the potential of the high potential node, having one terminal connected to the ground potential, a second terminal connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between a high potential node and a high potential hold transistor; means for charging and discharging a potential of a gate of the field relaxation transistor; and a second enhancement mode MOS transistor located between the high potential node and the discharge transistor, having a gate connected to a power supply.
Claim 18
Dependent Claim
161 words
A high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in a non-conducting state after the node is charged, having one terminal connected to a first input signal and a second terminal connected to the high potential node; an enhancement mode MOS transistor for discharging the potential of the high potential node, having one terminal connected to the ground potential, a second terminal connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between a high potential node and a high potential hold transistor; means for charging and discharging a potential of a gate of the field relaxation transistor; and a second enhancement mode MOS transistor located between the high potential node and the discharge transistor, having a gate connected to a power supply.
References Cited (Backward Citations)
US4388538A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |