Delay signal generating circuit

Claim 2

A digital circuit comprising a first node, a first series circuit including a first and a second enhancement type transistors connectable between a drain supply voltage and a source supply voltage, capacitor means coupled between said first node and a common junction point of said first series circuit, first means for connecting a gate of said first transistor to said first node, control means for operatively controlling said first series circuit in such a manner that a potential at said first node is raised above said drain supply voltage in absolute value by boot-strap effect, an output node, a second series circuit including a third and a fourth enhancement type transistors connectable between a drain supply voltage and a source supply voltage, a second means for connecting a common junction point of said second series circuit to said output node, a depletion type transistor, third means for connecting a drain of said depletion type transistor to said first node, fourth means for connecting a source of said depletion type transistor to a gate of said third transistor, and fifth means for supplying a gate of said depletion type transistor with a signal having the substantially same level as a signal at said common junction point of said first series circuit.

Claim 3

The circuit according to claim 1, further comprising sixth means for supplying a gate of said fourth transistor with a signal having the substantially same level as that at a gate of said second transistor.

Claim 4

The circuit according to claim 2, in which said control means includes means for supplying said first node with a first signal and means for supplying the gate of said second transistor with a second signal having a delayed opposite phase with respect to said first signal.

Claim 5

In a digital circuit comprising a boot-strap circuit operable with a drain supply voltage and a source supply voltage, said boot-strap circuit including a boot node whose potential is operatively raised above said drain supply voltage in absolute value and capacitor means having a first terminal connected to said boot node and a second terminal; an output node; and a first transistor of enhancement type responsive to the potential at said boot node for operatively supplying said output node with said drain supply voltage, the improvement comprising a second transistor of depletion type, means for connecting a drain of said second transistor to said boot node, means for connecting a source of said second transistor to a gate of said first transistor and means for supplying a gate of said second transistor with a signal having the substantially same level as a signal at said second terminal of said capacitor means.

Claim 6

In a digital circuit comprising a boot-strap circuit operable with a drain supply voltage and a source supply voltage, said boot-strap circuit including a boot node whose potential is operatively raised above said drain supply voltage in absolute value and capacitor means having a first terminal connected to said boot node and a second terminal; an output node; and a first transistor of enhancement type responsive to the potential at said boot node for operatively supplying said output node with said drain supply voltage, the improvement comprising a second transistor of depletion type, means for connecting a drain of said second transistor to said boot node, means for connecting a source of said second transistor to a gate of said first transistor and means for supplying a gate of said second transistor with a signal having the substantially same level as a signal at said second terminal of said capacitor means.

Claim 7

The circuit according to claim 4, further comprising a third transistor of enhancement type having a drain connected to said output node and a source connectable to said source supply voltage.

Claim 8

A digital circuit comprising a first node, a first and a second transistor of enhancement type, a drain of said first transistor being connectable to a drain supply voltage, a source of said first transistor and a drain of said second transistor being electrically common, a source of said second transistor being connectable to a source supply voltage, a gate of said first transistor being capacitively coupled to the source of said first transistor by a capacitance, control means for sequentially causing in response to each of a sequence signals, the gate of said first transistor to transition from a voltage near the source voltage toward a voltage near the drain voltage and to turn said first transistor on thereby causing the gate of said second transistor to transition from a voltage near the drain supply voltage to a voltage near the source supply voltage to turn the second transistor off thus causing the voltage at the gate of said first transistor to exceed said drain supply voltage as a result of the capacitive coupling from the source of said first transistor to the gate of said first transistor, an output node, a third and a fourth transistor of enhancement type, a drain of said third transistor being connectable to said drain supply voltage, a source of said third transistor and a drain of said fourth transistor being electrically common to said output node, a source of said fourth transistor being connectable to said source supply, means for connecting a gate of said fourth transistor to the gate of said second transistor, and transferring means for transferring a potential at the gate of said first transistor to the gate of said third transistor when a potential difference across said capacitor is smaller than a predetermined value.

Claim 9

A digital circuit comprising a first node, a first and a second transistor of enhancement type, a drain of said first transistor being connectable to a drain supply voltage, a source of said first transistor and a drain of said second transistor being electrically common, a source of said second transistor being connectable to a source supply voltage, a gate of said first transistor being capacitively coupled to the source of said first transistor by a capacitance, control means for sequentially causing in response to each of a sequence signals, the gate of said first transistor to transition from a voltage near the source voltage toward a voltage near the drain voltage and to turn said first transistor on thereby causing the gate of said second transistor to transition from a voltage near the drain supply voltage to a voltage near the source supply voltage to turn the second transistor off thus causing the voltage at the gate of said first transistor to exceed said drain supply voltage as a result of the capacitive coupling from the source of said first transistor to the gate of said first transistor, an output node, a third and a fourth transistor of enhancement type, a drain of said third transistor being connectable to said drain supply voltage, a source of said third transistor and a drain of said fourth transistor being electrically common to said output node, a source of said fourth transistor being connectable to said source supply, means for connecting a gate of said fourth transistor to the gate of said second transistor, and transferring means for transferring a potential at the gate of said first transistor to the gate of said third transistor when a potential difference across said capacitor is smaller than a predetermined value.

Claim 10

The circuit according to claim 6, in which said transferring means includes a fifth transistor of depletion type, means for connecting a drain of said fifth transistor to the gate of said first transistor, means for connecting a source of said fifth transistor to the gate of said third transistor, and means for supplying a gate of said fifth transistor with a signal having the substantially same potential as that at the drain of said second transistor.

Claim 11

A circuit comprising a bootstrap circuit operable with a first supply voltage and a second supply voltage, said bootstrap circuit including a boost node whose potential is operatively raised above said first supply voltage in absolute value and capacitor means having a first terminal adapted to be connected to said boost node and a second terminal; an output node; a first transistor responsive to the potential at said boost node for operatively supplying said output node with said first supply voltage; a second transistor adapted to be conducting when a potential difference across said capacitor means is smaller than a predetermined value; means for connecting one of a source and a drain of said second transistor to said boost node; means for connecting the other of a source and a drain of said second transistor to a gate of said first transistor; and means for supplying a gate of said second transistor with a signal having the same level as a signal at said second terminal of said capacitor means.

Claim 12

A circuit comprising a bootstrap circuit operable with a first supply voltage and a second supply voltage, said bootstrap circuit including a boost node whose potential is operatively raised above said first supply voltage in absolute value and capacitor means having a first terminal adapted to be connected to said boost node and a second terminal; an output node; a first transistor responsive to the potential at said boost node for operatively supplying said output node with said first supply voltage; a second transistor adapted to be conducting when a potential difference across said capacitor means is smaller than a predetermined value; means for connecting one of a source and a drain of said second transistor to said boost node; means for connecting the other of a source and a drain of said second transistor to a gate of said first transistor; and means for supplying a gate of said second transistor with a signal having the same level as a signal at said second terminal of said capacitor means.

Claim 13

The circuit according to claim 8, further comprising a third transistor connected in series with respect to said first transistor.

Claim 14

The circuit according to claim 8, in which said second transistor is of a depletion type while said first transistor is of an enhancement type.