Multiport memory with improved timing of word line selection

Claim 2

A multiport memory comprising: a storage section including bit lines and a word line, respectively defining rows and columns, a data transfer gate, and a dynamic memory cell; a serial port having a serial access function in a column direction of said storage section; a word line signal for selecting a word line of said storage section; and means for disabling said word line signal in response to a row address strobe signal and a data transfer gate signal at times when the row address strobe signal is raised in a transfer cycle in which data held by said memory cell is transferred to said serial port before the data transfer to said serial port is completed by said data transfer gate in response to the data transfer gate signal, wherein the word line signal is not disabled until the data transfer to said serial port is completed by said data transfer gate.

Claim 3

A memory according to claim 1, further comprising a timing generator for raising a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port.

Claim 4

A memory according to claim 1, wherein a data transfer gate signal is raised at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes a circuit for outputting a signal corresponding to the world line signal in accordance with an AND signal of a signal corresponding to the row address strobe signal and a signal corresponding to the data transfer gate signal.

Claim 5

A memory according to claim 1, wherein a data transfer gate signal is raised at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes waveform forming means for forming a waveform signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a circuit for outputting a signal corresponding to the word line signal in accordance with an AND signal of the waveform signal and the pulse signal.

Claim 6

A memory according to claim 1, wherein a data transfer gate signal is raised at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes waveform forming means for forming a wave form signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a flip-flop circuit responsive to the waveform signal and the pulse signal for outputting a signal corresponding to the word line signal.

Claim 7

A memory according to claim 1, wherein a data transfer gate signal is raised at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means enables or disables a signal corresponding to the row address strobe signal by a switching transistor for controlling a gate in response to the data transfer gate signal to output a signal corresponding to the word line signal.

Claim 8

A memory according to claim 1, wherein a data transfer gate signal is raised at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means comprises a circuit for switching a signal corresponding to the row address strobe signal in response to the data transfer gate signal to output a signal corresponding to the word line signal.

Claim 9

A memory according to claim 2, wherein said disabling means includes a circuit for outputting a signal corresponding to the world line signal in accordance with an AND signal of a signal corresponding to the row address strobe signal and a signal corresponding to the data transfer gate signal.

Claim 10

A memory according to claim 2, wherein said disabling means includes waveform forming means for forming a waveform signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a circuit for outputting a signal corresponding to the word line signal in accordance with an AND signal of the waveform signal and the pulse signal.

Claim 11

A memory according to claim 2, wherein said disabling means includes waveform forming means for forming a waveform signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a flip-flop circuit responsive to the waveform signal and the pulse signal for outputting a signal corresponding to the word line signal.

Claim 12

A memory according to claim 2, wherein said disabling means enables or disables a signal corresponding to the row address strobe signal by a switching transistor for controlling a gate in response to the data transfer gate signal to output a signal corresponding to the word line signal.

Claim 13

A memory according to claim 2, wherein said disabling means comprises a circuit for switching a signal corresponding to the row address strobe signal in response to the data transfer gate signal to output a signal corresponding to the word line signal.

Claim 14

A multiport memory comprising: a memory cell array, including bit lines and word lines, respectively defining rows and columns of said array; a row address buffer; a row address decoder; a column address buffer; a column address decoder and selector; an input/output data buffer; a data transfer gate; a serial data register; a serial address counter; a serial decoder and selector; a serial input/output data buffer; and a word line signal for selecting a word line of said memory cell array; and a timing generator including means for disabling said word line signal in response to a row address strobe signal and a data transfer gate signal at times when the row address strobe signal is raised in a transfer cycle in which data held by said memory cell is transferred to said serial port before the data transfer to said serial port is completed by said data transfer gate in response tot he data transfer gate signal, wherein the word line signal is not disabled until the data transfer to said serial port is completed by said data transfer gate.

Claim 15

A multiport memory comprising: a memory cell array, including bit lines and word lines, respectively defining rows and columns of said array; a row address buffer; a row address decoder; a column address buffer; a column address decoder and selector; an input/output data buffer; a data transfer gate; a serial data register; a serial address counter; a serial decoder and selector; a serial input/output data buffer; and a word line signal for selecting a word line of said memory cell array; and a timing generator including means for disabling said word line signal in response to a row address strobe signal and a data transfer gate signal at times when the row address strobe signal is raised in a transfer cycle in which data held by said memory cell is transferred to said serial port before the data transfer to said serial port is completed by said data transfer gate in response tot he data transfer gate signal, wherein the word line signal is not disabled until the data transfer to said serial port is completed by said data transfer gate.

Claim 16

A memory according to claim 13, wherein the timing generator raises a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes a circuit for outputting a signal corresponding to the world line signal in accordance with an AND signal of a signal corresponding to the row address strobe signal and a signal corresponding to the data transfer gate signal.

Claim 17

A memory according to claim 13, wherein the timing generator raises a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes waveform forming means for forming a waveform signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a circuit for outputting a signal corresponding to the word line signal in accordance with an AND signal of the waveform signal and the pulse signal.

Claim 18

A memory according to claim 13, wherein the timing generator raises a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means includes waveform forming means for forming a waveform signal in response to the row address strobe signal, pulse generating means for generating a pulse signal in response to the data transfer gate signal, and a flip-flop circuit responsive to the waveform signal and the pulse signal for outputting a signal corresponding to the word line signal.

Claim 19

A memory according to claim 13, wherein the timing generator raises a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means enables or disables a signal corresponding to the row address strobe signal by a switching transistor for controlling a gate in response to the data transfer gate signal to output a signal corresponding to the word line signal.

Claim 20

A memory according to claim 13, wherein the timing generator raises a data transfer gate signal at a leading edge of an output enable signal when the data held by said memory cell is transferred to said serial port; and said disabling means comprises a circuit for switching a signal corresponding to the row address strobe signal in response to the data transfer gate signal to output a signal corresponding to the word line signal.