EP0188134A2
Expired / Lapsed
EP
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Semiconductor memory device having serial data input and output circuit
Assignee: Fujitsu VLSI Ltd
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Filing: 1985-12-31
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Granted: —
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Expires: 2005-12-31
Abstract
Abstract A dual-port type semiconductor memory device having a serial data input and output circuit (200) provided outside of a memory cell array (1) and operable for high-speed serial data input and output of data in addition to random data access. The semiconductor memory device includes a single decoding circuit (5) triggering at least one gate for transferring data to be stored into or read from the memory cell array in a random data access mode and setting a single bit to a corresponding shift register (24) in the serial data input and output circuit in a serial data input and output operation mode. Preferably, the decoding circuit is operated only during a time for operatively connecting bit lines and latch circuits in the serial data input and output circuit in the serial data input and output operation mode. The serial data input and output circuit is operable independently from the memory cell array, except during the time for operatively connecting the bit lines and the latch circuits through transfer gates, for serially inputting data to or outputting data from the latch circuits through serial data bus by sequentially triggering the serial gates from a certain gate designated by the corresponding shift register in response to the decoding circuit.
Inventors
- 👤 Masaaki Fujitsu Seto-Ryo 201 Noguchi
- 👤 Junji Ogawa
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; G11C11/409; G11C11/4093; G11C11/4096
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
335 words
A semiconductor memory device comprising: memory cell array means (1) including a plurality of memory cells (MC) arranged in a matrix form with a plurality of bit lines (BL, EL) and a plurality of word lines (WL, WL); means (6), operatively connected to said memory cell array means, for selecting one of said word lines in response to an address signal (RA); data bus means (10); a plurality of gates (3, 4), operatively connected between said bit lines and data bus means (10), for transferring data to be stored or read between said bit lines and said data bus means; means (200) for serially inputting or outputting data, including a plurality of transfer gates (21), operatively connected to said bit lines and operable in a group in response to a transfer clock pulse (TCLK), a plurality of latch circuits (22) operatively connected to said transfer gates and holding data to be stored or read, serial data bus means (20), a plurality of serial gates (23), having terminals operatively connected to said latch circuits and operatively connected to said serial data bus means (20), and a plurality of shift registers (24), connected in cascade to form a ring counter, for triggering serial gates,; and decoding means (5) operatively connected to said gates (3, 4) for triggering at least one of said gates in response to another address signal (CA) in a random access operation mode and operatively connected to said shift registers setting decoded data of the column address signal on said shift registers in response to the column address signal in a serial data input and output operation mode; said serial data input and output means operable independently from said memory cell array, except during a time for operatively connecting said bit lines and said latch circuits through said transfer gates, for serially inputting data to or outputting data from said latch circuits through said serial data bus means by sequentially triggering said serial gates from a certain gate designated by said corresponding shift register.
Claim 2
Dependent Claim
335 words
A semiconductor memory device comprising: memory cell array means (1) including a plurality of memory cells (MC) arranged in a matrix form with a plurality of bit lines (BL, EL) and a plurality of word lines (WL, WL); means (6), operatively connected to said memory cell array means, for selecting one of said word lines in response to an address signal (RA); data bus means (10); a plurality of gates (3, 4), operatively connected between said bit lines and data bus means (10), for transferring data to be stored or read between said bit lines and said data bus means; means (200) for serially inputting or outputting data, including a plurality of transfer gates (21), operatively connected to said bit lines and operable in a group in response to a transfer clock pulse (TCLK), a plurality of latch circuits (22) operatively connected to said transfer gates and holding data to be stored or read, serial data bus means (20), a plurality of serial gates (23), having terminals operatively connected to said latch circuits and operatively connected to said serial data bus means (20), and a plurality of shift registers (24), connected in cascade to form a ring counter, for triggering serial gates,; and decoding means (5) operatively connected to said gates (3, 4) for triggering at least one of said gates in response to another address signal (CA) in a random access operation mode and operatively connected to said shift registers setting decoded data of the column address signal on said shift registers in response to the column address signal in a serial data input and output operation mode; said serial data input and output means operable independently from said memory cell array, except during a time for operatively connecting said bit lines and said latch circuits through said transfer gates, for serially inputting data to or outputting data from said latch circuits through said serial data bus means by sequentially triggering said serial gates from a certain gate designated by said corresponding shift register.
Claim 3
Dependent Claim
37 words
A semiconductor memory device according to claim 1, wherein said decoding means is operated only during said time for operatively connecting said bit lines and said latch circuits in said serial data input and output operation mode.
Claim 4
Dependent Claim
51 words
A semiconductor memory device according to claim 2, wherein said data bus means (10) includes one or more data buses and said serial data bus means (20) also includes one or more data buses, the number of said data bus means being equal to the number of said serial data buses.
Claim 5
Dependent Claim
78 words
A semiconductor memory device according to claim 3, wherein said decoding means (5) includes a predecoding circuit (50) and a plurality of decoders (5"), said predecoding circuit outputting a plurality of predecoded signals (CDS), defined by a part of said another address signal, to said decoders, each of said decoders including a plurality of decoding circuits, operatively connected to said gates (3, 4) and said shift registers (24), defined by the remaining part of said another address signal.
Claim 6
Dependent Claim
68 words
A semiconductor memory device according to claim 4, wherein said gates (3, 4) are operatively connected between said bit lines and said data bus means (10) so that a plurality of said gates, defined by said number of said data buses, are triggered in a group by a signal from said decoding means, to transfer a plurality of data between said data bus means and said bit lines.
Claim 7
Dependent Claim
92 words
A semiconductor memory device according to claim 5, wherein the number of said plurality of shift registers is equal to the number of said plurality of decoding circuits in each decoder, each shift register triggering a plurality of said serial gates, defined by said number of said serial data buses, in a group, and - wherein said serial gates are operatively connected between said serial data bus means and said latch circuits so that a plurality of data are transferred in parallel between said serial data bus means and said latch circuits.
Claim 8
Dependent Claim
17 words
A semiconductor memory device according to claim 6, wherein each of said latch circuits includes a flip-flop.
Claim 9
Dependent Claim
44 words
A semiconductor memory device according to claim 6, wherein each of said shift registers is operated in response to the output from said decoding means when a pulse for designating the serial data input and output operation mode is added to said shift registers.
Claim 10
Dependent Claim
64 words
A semiconductor memory device according to claim 8, wherein each of said shift registers is formed by a two-phase ratio-type shift register, a phase clock for shifting one bit in a shift register to an adjacent shift register being applied to said shift register and another phase clock, shifted approximately 180° in phase from said phase clock, being applied to said adjacent shift register.
Claim 11
Dependent Claim
22 words
A semiconductor memory device according to claim 3, wherein each data bus in said data bus means includes a single bus line.
Claim 12
Dependent Claim
24 words
A semiconductor memory device according to claim 3, wherein each data bus in said data bus means includes a pair of complementary bus lines.
Claim 13
Dependent Claim
22 words
A semiconductor memory device according to claim 3, wherein each bus in said serial data bus means includes a single bus line.
Claim 14
Dependent Claim
24 words
A semiconductor memory device according to claim 3, wherein each bus in said serial data bus means includes a pair of complementary bus lines.
Claim 15
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein the circuit construction is determined so that lines between said decoding means (5) and said plurality of gates (3, 4) and lines between said decoding means and said shift registers (24) are minimized in "length in a semiconductor memory device chip.
Claim 16
Dependent Claim
45 words
A semiconductor memory device according to claim 14, wherein said circuit construction is determined so that lines between said bit lines and said transfer gates (21) and lines between said transfer gates (21) and said latch circuits (22) are minimized in length on said chip.
Claim 17
Dependent Claim
60 words
A semiconductor memory device according to claim 1, wherein said memory cell array means includes one or more memory cell arrays and wherein said serial data input and output means includes one or more circuits for serially inputting and outputting data, the number of said memory cell arrays being equal to the number of said serial input and output circuits.
Claim 18
Dependent Claim
25 words
A semiconductor memory device according to claim 16, wherein each memory cell array of said memory cell array means includes dynamic random-access memory (RAM) cells.
Claim 19
Dependent Claim
19 words
A semiconductor memory device according to claim 17, wherein said dynamic RAM cells are of an open-bit line form.
Claim 20
Dependent Claim
19 words
A semiconductor memory device according to claim 17, wherein said dynamic RAM cells are of a folded-bit line form.
References Cited (Backward Citations)
No citation records indexed.
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