Multi-port memory system

Claim 2

A multiport memory system which has a plurality of data input/output ports, a plurality of memory banks, and a switching network for connecting the ports and the memory banks and in which pages are each stored across all the memory banks and an address is specified page by page from each input/output port, characterized in that the page address is transferred and set by way of a data line of the switching network and the address is calculated in each memory bank.

Claim 3

A multiport memory system according to claim 1, characterized in that the switching network has data transfer buses in two directions and the buses are bit-sliced and formed by programmable logic arrays and counters.

Claim 4

A multiport memory system according to claim 1 or 2, characterized in that each memory bank has a shift register for rotating the switching of the switching network to transfer the page address between the memory banks in synchronization with the switching of the ports and for transporting the address to the next memory bank, a latch for fixing the page address during the shift operation of the shift register, and a counter for incrementing the page address by one during its transportation.

Claim 5

A multiport memory system which has a plurality of data input/output ports, each specifying an address page by page, a plurality of memory banks, and a switching network for rotating the switching of the connections between the ports and the memory banks, each memory bank having a shift register for transporting the address to the next memory bank, a latch for fixing the page address during the shift operation of the shift register, a counter for incrementing the page address one by one during the shift operation, and a counter for incrementing an address of a block by one upon each rotation of the switching of the connections between the ports and the memory banks, and in which the page address is transported between the memory banks in synchronization with the switching of the ports, the page is stored across all the memory banks, the page address is transferred and set by way of a data line of the switching network, and an address calculation is performed in each memory bank so that continuous data can be read out of and written in the same page from the plurality of ports, characterized in that a buffer is provided between the switching network and each port, the buffer has an address calculating adder for calculating an in-page address t9 be transferred to and from the switching network, from the sum of the value of a switching network change-over counter and the number of each port, whereby the access is started independently of the connections between the memory banks and the ports.

Claim 6

A multiport memory system which has a plurality of data input/output ports, each specifying an address page by page, a plurality of memory banks, and a switching network for rotating the switching of the connections between the ports and the memory banks, each memory bank having a shift register for transporting the address to the next memory bank, a latch for fixing the page address during the shift operation of the shift register, a counter for incrementing the page address one by one during the shift operation, and a counter for incrementing an address of a block by one upon each rotation of the switching of the connections between the ports and the memory banks, and in which the page address is transported between the memory banks in synchronization with the switching of the ports, the page is stored across all the memory banks, the page address is transferred and set by way of a data line of the switching network, and an address calculation is performed in each memory bank so that continuous data can be read out of and written in the same page from the plurality of ports, characterized in that a buffer is provided between the switching network and each port, the buffer has an address calculating adder for calculating an in-page address t9 be transferred to and from the switching network, from the sum of the value of a switching network change-over counter and the number of each port, whereby the access is started independently of the connections between the memory banks and the ports.