Multi-port memory

Claim 2

Memory array with decoders having cells each of which is separately addressable from a plurality of write lines and is readable by a plurality of sets of bit lines, characterized by a low order and higher order word decoders (12-14) coupled to each cell (11) of the array (10), a low order and higher order read heads (21-23) coupled to each cell of the array, via said plurality of bit lines, said higher order read heads being equal in number to the number of higher order word decoders, at least one multiplexer circuit coupled to each of said higher order read heads (22, 23), and address comparison means (24-26) coupled to said higher order word decoders (13, 14) and said higher order read heads.

Claim 3

The memory array of claim 1, characterized in that address comparison means (24-26), in the event of a compare between said addresses, provides a signal to said higher order word decoders (13, 14) to disable selected ones of said higher order word decoders and inhibit selected ones of said higher order read heads (22, 23) from reading more than one set of simultaneously addressed bit lines from the cell (11) while switching the inhibited higher order read heads to output read lines having the same address as the low order word decoder (12).

Claim 4

The memory array of claim 1, characterized in that each of said sets of bit lines comprises a differential pair of bit lines, and each of said read heads comprises a pair of read transistors, each of which is coupled to one of said pair of bit lines and to a differential amplifier, said differential amplifier being coupled to an output read line.

Claim 5

The memory array of claim 1, characterized in that each of said read heads (21-23) comprise a read transistor coupled to a respective bit line set and to an output amplifier.

Claim 6

The memory array of claim 1, characterized in that said multiplexer circuit comprises means for inhibiting the bit line set coupled to said read head, and means for transferring the input to said low order read head to the output amplifier of the read head to which the multiplexer is coupled.

Claim 7

The memory array of claim 1, characterized in that said low order and said higher order read heads are arranged serially, said low order read head being the first in said series, each of said higher order read head being coupled to one multiplexer more than the number of multiplexers to which the preceeding read head is coupled.

Claim 8

The memory array of claims 1-6, characterized by a plurality of sets of word decoders (12-14) coupled to each cell (11) of the array (10), a plurality of sets of high to low order read heads (21-23) equal in number to the number of word decoders (12, 14) coupled to the cell of the array, and having a plurality of output read lines equal to the number of said word decoders, at least one multiplexer, coupled to each of the higher order read heads (22, 23), and a plurality of comparator means (24-26) for comparing the address inputs to the word decoders, said comparator means being coupled to the word decoders and the multiplexers and in the event of a compare disabling selected ones of word decoders, and inhibiting selected ones of the read heads, from reading selected ones of said bit lines, said multiplexer switching the output data of the cell to output read lines having the same address as said uninhibited one of said word decoders.

Claim 9

The memory array of claim 7, characterized by comparator means coupled to the word decoders and the multiplexer for comparing the address inputs to the word decoders and in the event of a compare disabling selected ones of the word decoders, and disabling selected ones of the higher order read heads, said multiplexer switching the output data of the cell to output read lines having the same address as said uninhibited one of said word decoders.