Process for the reception of a binary digital signal

Claim 1

A process for receiving a binary digital signal, which may also have phase shifts, using a clock signal, whose frequency is plesiochronous with or equal to the bit rate of the digital signal and whose phase difference is selected arbitrarily with respect to the digital signal, the process comprising the steps of: applying the clock signal to serially connected delay elements with approximately constant delays; deriving a series of n+p+l clock pulses from the clock signal, through transmission over n principal ones of said delay elements with approximately equal principal delays and a total principal delay of at least one clock period and over p additional ones of said delay elements with additional delays equal to the principal delays ( t1), where n is an integer greater than three and p is an integer greater than or equal to zero; deriving a sequence of shorter pulses from the rising and/or falling edges of the clock pulses, each of said shorter pulses having a duration that is greater than a principal delay and, given large values of n, is big enough so that logic elements can be driven by said shorter pulses which are short with respect to the clock period; deriving read pulses and reset pulses from the rising and/or falling edges of the digital signal, with a duration that is small compared with a clock period, but large enough so that logic elements can be driven by said read pulses and said reset pulses; storing in memory elements during the occurrence of a read pulse a simultaneously occurring shorter pulse or pulses of the sequence of shorter pulses, after the memory elements have been cleared immediately before with the resetting pulses; switching through a clock for every memory element that has stored a pulse of the sequence of shorter pulses, which originates from a delay element that is downstream of the delay element from whose clock the stored pulse was derived; blocking a clock from every memory element that has not stored a pulse; OR-linking the clocks that have been switched through and blocked to from an OR-linked input clock; selecting the clock or clocks that has/have been switched through from the principal and additional delay elements that are connected downstream in each case in such a manner that the rising and/or falling edge of the OR-linked input clock formed from the clocks that have been switched through and blocked arrives delayed by about half a clock period with respect to the edge of the digital signal; and reading the digital signal as an output digital signal responsive to the rising or falling edge of the input clock.