Output circuit having high speed operation and low power dissipation

Claim 1

An output circuit comprising: a first MOS transistor, a source-drain path of which is connected between a first potential and an output terminal; a level shift bipolar transistor connected between said first potential and a gate of said first MOS transistor; a second MOS transistor, a source-drain path of which is connected between a control terminal of said bipolar transistor and a second potential, and a gate of which receives a first control signal; a constant voltage element connected between the gate of said first MOS transistor and said output terminal; a third MOS transistor having an element size smaller than that of a fourth MOS transistor, a source-drain path of said third MOS transistor being connected between a node of said gate of said first MOS transistor, a first collector of said bipolar transistor, and said constant voltage element, and said second potential, and a gate of said third MOS transistor receiving a second control signal which is an inversion of the first control signal; and the fourth MOS transistor, a source-drain path of which is connected between said output terminal and said second potential, and a gate of which receives a third control signal obtained by delaying the second control signal by a predetermined period of time.