Output circuit for a semiconductor device for reducing rise time of an output signal

Claim 2

An output circuit for generating an output signal having at least two voltage levels in response to an input signal having corresponding voltage levels, comprising: first circuit means for generating a first signal, the first signal changing between high and low impedance levels in response to changes between the two voltage levels of the input signal; second circuit means responsive to the input signal for supplying a second signal, the second signal changing between high and low impedance levels, and including control circuit means for delaying the changing of the impedance level of the second signal until after the impedance level of the first signal has changed; and means for combining the first and the second signals to produce the output signal; and wherein the control means delays the change of the second signal from the high impedance level to the low impedance level until after the change of the first signal from the low impedance level to the high impedance level; the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; the control circuit means supplies a control signal to the gate electrode of the second MOS transistor for controlling the conductivity of the MOS transistor; and the control circuit means includes inverter circuit means for inverting the input signal, delay means for delaying the input signal and NAND circuit means for producing a logic signal in response to the delay means and the inverter circuit means.

Claim 3

An output circuit for generating an output signal having at least two voltage levels in response to an input signal having corresponding voltage levels, comprising: first circuit means for generating a first signal, the first signal changing between high and low impedance levels in response to changes between the two voltage levels of the input signal; second circuit means responsive to the input signal for supplying a second signal, the second signal changing between high and low impedance levels, and including control circuit means for delaying the changing of the impedance level of the second signal until after the impedance level of the first signal has changed; and means for combining the first and the second signals to produce the output signal; and wherein the control means delays the change of the second signal from the high impedance level to the low impedance level until after the change of the first signal from the low impedance level to the high impedance level; the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; the control circuit means supplies a control signal to the gate electrode of the second MOS transistor for controlling the conductivity of the second MOS transistor; and the control circuit means includes delay means for delaying the input signal, inverter circuit means for inverting the input signal, and AND circuit means for producing a logic signal in response to the delay means and the inverter circuit means.

Claim 4

An output circuit for generating an output signal having at least two voltage levels in response to an input signal having corresponding voltage levels, comprising: first circuit means for generating a first signal, the first signal changing between high and low impedance levels in response to changes between the two voltage levels of the input signal; second circuit means responsive to the input signal for supplying a second signal, the second signal changing between high and low impedance levels, and including control circuit means for delaying the changing of the impedance level of the second signal until after the impedance level of the first signal has changed; and means for combining the first and the second signals to produce the output signal; and wherein the control means delays the change of the second signal from the high impedance level to the low impedance level until after the change of the first signal from the low impedance level to the high impedance level; the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; the control circuit means supplies a control signal to the gate electrode of the second MOS transistor for controlling the conductivity of the second MOS transistor; and the control circuit means includes delay means for delaying the input signal, inverter circuit means for inverting the input signal, and AND circuit means for producing a logic signal in response to the delay means and the inverter circuit means.

Claim 5

An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, in which the second voltage level of the input signal continues for a prescribed duration of time, comprising: first circuit means responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal; second circuit means responsive to the input signal for supplying a second signal including a low impedance portion after the duration of the second voltage level of the input signal; and means for combining the first and the second signals to produce the output signal; and wherein the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; control signal output circuit means for supplying a control signal to the gate electrode of the second MOS transistor controls the conductivity of the second MOS transistor; and the control signal output circuit means comprises delay circuit means for delaying the input signal, inverter circuit means for inverting the input signal and NAND circuit means for producing a logic signal in response to the delay circuit means and the inverter circuit means.

Claim 6

An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, in which the second voltage level of the input signal continues for a prescribed duration of time, comprising: first circuit means responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal; second circuit means responsive to the input signal for supplying a second signal including a low impedance portion after the duration of the second voltage level of the input signal; and means for combining the first and the second signals to produce the output signal; and wherein the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; control signal output circuit means for supplying a control signal to the gate electrode of the second MOS transistor controls the conductivity of the second MOS transistor; and the control signal output circuit means comprises delay circuit means for delaying the input signal, inverter circuit means for inverting the input signal and NAND circuit means for producing a logic signal in response to the delay circuit means and the inverter circuit means.

Claim 7

An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, in which the second voltage level of the input signal continues for a prescribed duration of time, comprising: first circuit means responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal; second circuit means responsive to the input signal for supplying a second signal including a low impedance portion after the duration of the second voltage level of the input signal; and means for combining the first and the second signals to produce the output signal; and wherein the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; control signal output circuit means for supplying a control signal to the gate electrode of the second MOS transistor controls the conductivity of the second MOS transistor; and the control signal output circuit means includes delay circuit means for delaying the input signal, inverter circuit means for inverting the input signal and AND circuit means for producing a logic signal in response to the delay circuit means and the inverter circuit means.

Claim 8

An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, in which the second voltage level of the input signal continues for a prescribed duration of time, comprising: first circuit means responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal; second circuit means responsive to the input signal for supplying a second signal including a low impedance portion after the duration of the second voltage level of the input signal; and means for combining the first and the second signals to produce the output signal; and wherein the first circuit means comprises a first MOS transistor of one conductivity type having a gate electrode for receiving the input signal; the second circuit means includes a second MOS transistor of a second conductivity type having a gate electrode; control signal output circuit means for supplying a control signal to the gate electrode of the second MOS transistor controls the conductivity of the second MOS transistor; and the control signal output circuit means includes delay circuit means for delaying the input signal, inverter circuit means for inverting the input signal and AND circuit means for producing a logic signal in response to the delay circuit means and the inverter circuit means.