EP0238358A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Buffer circuit
Assignee: Toshiba Corp
•
Filing: 1987-03-20
•
Granted: —
•
Expires: 2007-03-20
Abstract
Abstract A buffer circuit is disclosed which includes an input node (D1) for receiving an input voltage and an output node (D-out) for providing an output voltage in response to the input voltage load transistor means (Q20, Q21) for connecting the output node (D-out) to a first predetermined voltage (VCC) in response to a first level of the input voltage. drive transistor means (Q27, Q28) for connecting the output node to a second predetermined voltage in response to a second level of the input voltage, said output node (D-out) being connected to only one of said predetermined voltages at a time and means (17, 20, 21, 24) for reducing the rate of increase of output current at said output node when the voltage at the output node changes between said levels.
Inventors
- 👤 Kenichi C/O Patent Division Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K19/0008; H03K19/0013; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
129 words
A buffer circuit comprising an input node (Dl) for receiving an input voltage and an output node (D-out) for providing an output voltage in response to the input voltage load transistor means (Q20, Q21) for connecting the output node (D-out) to a first predetermined voltage (VCC) in response to a first level of the input voltage, drive transistor means (Q27, Q28) for connecting the output node to a second predetermined voltage in response to a second level of the input voltage, said output node (D-out) being connected to only one of said predetermined voltages at a time and characterised by means (17, 20, 21, 24) for reducing the rate of increase of output current at said output node when the voltage at the output node changes between said levels.
Claim 2
Dependent Claim
129 words
A buffer circuit comprising an input node (Dl) for receiving an input voltage and an output node (D-out) for providing an output voltage in response to the input voltage load transistor means (Q20, Q21) for connecting the output node (D-out) to a first predetermined voltage (VCC) in response to a first level of the input voltage, drive transistor means (Q27, Q28) for connecting the output node to a second predetermined voltage in response to a second level of the input voltage, said output node (D-out) being connected to only one of said predetermined voltages at a time and characterised by means (17, 20, 21, 24) for reducing the rate of increase of output current at said output node when the voltage at the output node changes between said levels.
Claim 3
Dependent Claim
34 words
A device as claimed in claim 1 wherein the load transistor means includes a plurality of laod transistors (Q20, Q21, Q80) coupled in parallel between the output node and the first predetermined voltage (Vcc).
Claim 4
Dependent Claim
36 words
3 . A device as claimed in claim 1 wherein the drive transistor (Q27, Q28, Q82) means includes a plurality of drive transistors coupled in parallel between the output node and the second predetermined voltage (Vss).
Claim 5
Dependent Claim
90 words
A device as claimed in claim 1 wherein the reducing means includes first and second delay means (17, 20, 21, 24) responsive to the input current for alternately switching the load and drive transistors (Q20, Q21, Q27, Q28) from a second state to a first state in sequence at predetermined time intervals, and switching the load and drive transistors (Q20, Q21, Q27, Q28) from a first state to a second state simultaneously, the state of the load transistors (Q20, Q21) being opposite to that of the drive transistors (Q27, Q28).
Claim 6
Dependent Claim
128 words
A device as claimed in claim 4 wherein the first and second delay means (17, 20, 21, 24) each have corresponding threshold voltages, and the buffer circuit also includes: a first inverter means (15) having a predetermined first threshold voltage for inverting the input current and supplying the inverted current to the first delay means (17, 20), the first threshold voltage being lower than the threshold voltage of the first and second delay means (17, 20, 21, 24); and a second inverter 916) means having a predetermined second threshold voltage for inverting the input current and supplying the inverted current to the second delay means (21, 24), the second threshold voltage being higher than the threshold voltage of the first and second delay means (17, 20, 21, 24).
Claim 7
Dependent Claim
73 words
A device as claimed in claim 5 wherein the first inverter means (15) includes a first p channel transistor (Qll) and a first n channel transistor (Q12), the two transistors (Qll, Q12) being coupled in series to the power source, and the second inverter means (16) includes a second p channel transistor (Q13) and a second n channel transistor (Q14), the two transistors (Q13, Q14) being coupled in series to the power source.
Claim 8
Dependent Claim
59 words
A device as claimed in claim 6 wherein each transistor has a predetermined gate length, and the gate length of the first p channel transistor (Qll) is smaller than that of the first n channel transistor (Ql2) and the gate length of the second p channel transistor (Q13) is larger than that of the second n channel transistor (Q14).
Claim 9
Dependent Claim
56 words
8 . A device as claimed in claim 4 wherein the first delay means (17, 20) includes third inverter means (17) for switching one of the load transistors in response to the input current and third delay means (20) for switching another of the load transistors at predetermined time intervals in response to the input current.
Claim 10
Dependent Claim
55 words
A device as claimed in claim 4 wherein the second delay means (21, 24) includes fourth inverter means (21) for switching the one of the drive transistors in response to the input current and fourth delay means (24) for switching another of the drive transistors at predetermined time intervals in response to the input current.
Claim 11
Dependent Claim
93 words
A device as claimed in claim 8 wherein the third delay means (20) includes a third p channel, third and fourth n channel transistors (Q17, Q18, Q19), and a first delay element (18, 19), each transistor having a corresponding input junction, the transistors (Q17, Q18, Q19) being coupled in series to the power source, the first delay element (18, 19) being coupled between the input junction of the fourth n channel transistor (Q19) and the input junctions of the third p channel transistor (Q17) and the third n channel transistor (Q1 8 ).
Claim 12
Dependent Claim
57 words
A device as claimed in claim 10 wherein the first delay element (18, 19) has a corresponding first output signal, and the first delay means also includes fifth delay means (80) for switching another of the load transistors after a predetermined time interval in response to the first output signal of the first delay element (18, 19).
Claim 13
Dependent Claim
94 words
A device as claimed in claim 9 wherein the fourth delay means (24) includes a fifth n channel, fourth and fifth p channel transistors (Q24, Q25, Q26), and a second delay element (22, 23), each transistor (Q24, Q25, Q26) having a corresponding input junction, the transistors (Q24, Q25, Q26) being coupled in series to the power source, the second delay element (22, 23) being coupled between the input junction of the fourth p channel transistor (Q26) and the input junctions of the fifth p channel transistor (Q25) and the fifth n channel transistor (Q24).
Claim 14
Dependent Claim
57 words
A device as claimed in claim 12 wherein the second delay element (22, 23) has a corresponding second output signal, and the second delay means also includes sixth delay means (86) for switching another of the load transistors after a predetermined time interval in response to the second output signal of the second delay element (22, 23).
Claim 15
Dependent Claim
19 words
A device as claimed in claim 10 or claim 12 wherein the delay element includes an inverter (18, 19).
Claim 16
Dependent Claim
22 words
A device as claimed in claim 10 or claim 12 wherein the delay element includes a resistor (60) and a capacitor (62).
Claim 17
Dependent Claim
29 words
A device as claimed in claim 10 or claim 12 wherein the delay element includes a depletion type MOS transistor (Q70), the gate and drain thereof being coupled together.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.