Patent US2792733A successfully refreshed from Google Patents.
Patent US2906415A successfully refreshed from Google Patents.
Patent US4994404A successfully refreshed from Google Patents.
US4994404A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming a lightly-doped drain (LDD) structure in a semiconductor device
Assignee: Motorola Solutions Inc
•
Filing: 1989-08-28
•
Granted: 1991-02-19
•
Expires: 2009-08-28
Abstract
Abstract A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer. The sidewall spacer is then removed completing the LDD structure.
Inventors
- 👤 David Y. Sheng
- 👤 Yasunobu Kosa
- 👤 Andrew J. Urquhart
- 👤 Mark J. Cullen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
206 words
A method for forming a lightly-doped drain in a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type and having an active region intermediate to a first and a second isolation region; forming a thin dielectric layer overlying said active region; forming a transistor gate in a central portion of said active region overlying said dielectric layer, said gate having horizontal surface and bounded by a vertical surface; forming an oxidation layer to overlie said active region and said transistor gate; forming a lightly-doped impurity region of a second conductivity type in said active region using said gate and said first and second isolation regions as a doping mask; depositing by plasma enhanced chemical vapor deposition a conformal layer of amorphous carbon to overlie said substrate; anisotropically etching said conformal layer of amorphous carbon by oxygen plasma reactive ion etching to remove said layer from said horizontal surface and leave a portion of said amorphous carbon covering said vertical surface to form a sidewall spacer; forming a highly doped impurity region of a second conductivity type in said active region using said sidewall spacer and said first and second active regions as a doping mask; and removing said sidewall spacer.
Claim 2
Independent Claim
206 words
A method for forming a lightly-doped drain in a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type and having an active region intermediate to a first and a second isolation region; forming a thin dielectric layer overlying said active region; forming a transistor gate in a central portion of said active region overlying said dielectric layer, said gate having horizontal surface and bounded by a vertical surface; forming an oxidation layer to overlie said active region and said transistor gate; forming a lightly-doped impurity region of a second conductivity type in said active region using said gate and said first and second isolation regions as a doping mask; depositing by plasma enhanced chemical vapor deposition a conformal layer of amorphous carbon to overlie said substrate; anisotropically etching said conformal layer of amorphous carbon by oxygen plasma reactive ion etching to remove said layer from said horizontal surface and leave a portion of said amorphous carbon covering said vertical surface to form a sidewall spacer; forming a highly doped impurity region of a second conductivity type in said active region using said sidewall spacer and said first and second active regions as a doping mask; and removing said sidewall spacer.
Claim 3
Independent Claim
201 words
A method for forming a lightly-doped drain in a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type and having an active region intermediate to a first and a second isolation region; forming a thin dielectric layer overlying said active region; forming a transistor gate in a central portion of said active region overlying said dielectric layer, said gate having a horizontal surface and bounded by a vertical surface; forming an oxidation layer to overlie said active region and said transistor gate; forming a lightly-doped impurity region of a second conductivity type in said active region using said gate and said first and second isolation regions as a doping mask; depositing by plasma enhanced chemical vapor deposition a conformal layer of amorphous carbon to overlie said substrate; anisotropically etching said conformal layer of amorphous carbon to remove said layer from said horizontal surface and leave a portion of said amorphous carbon covering said vertical surface to form a sidewall spacer; forming a highly doped impurity region of a second conductivity type in said active region using said sidewall spacer and said first and second active regions as a doping mask; and removing said sidewall spacer.
Claim 4
Independent Claim
201 words
A method for forming a lightly-doped drain in a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type and having an active region intermediate to a first and a second isolation region; forming a thin dielectric layer overlying said active region; forming a transistor gate in a central portion of said active region overlying said dielectric layer, said gate having a horizontal surface and bounded by a vertical surface; forming an oxidation layer to overlie said active region and said transistor gate; forming a lightly-doped impurity region of a second conductivity type in said active region using said gate and said first and second isolation regions as a doping mask; depositing by plasma enhanced chemical vapor deposition a conformal layer of amorphous carbon to overlie said substrate; anisotropically etching said conformal layer of amorphous carbon to remove said layer from said horizontal surface and leave a portion of said amorphous carbon covering said vertical surface to form a sidewall spacer; forming a highly doped impurity region of a second conductivity type in said active region using said sidewall spacer and said first and second active regions as a doping mask; and removing said sidewall spacer.
References Cited (Backward Citations)
US4590663A
Cited
US4642878A
Cited
US4740484A
Cited
US4744859A
Cited
US4728617A
Cited
US4764477A
Cited
US4838991A
Cited
US4855247A
Cited
US4886765A
Cited
US4876213A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |