Patent US4989224A successfully refreshed from Google Patents.
US4989224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coincidence circuit
Assignee: Fujifilm Business Innovation Corp
•
Filing: 1988-11-29
•
Granted: 1991-01-29
•
Expires: 2008-11-29
Abstract
Abstract A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the "1" input bits have corresponding "1" clock bits. Each "1" detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.
Inventors
- 👤 Mitsumasa Narahara
- 👤 Kazumi Yamauchi
- 👤 Yuji Yatsuda
- 👤 Shinichi Yasunaga
- 👤 Fujio Moriguchi
- 👤 Nobuhisa Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
223 words
A current control circuit for controlling the supply of current to a plurality of resistors for use in a thermal print head in a printing of an image corresponding to n-bit image data comprising: a counter for producing n-bit count data; a coincidence circuit for judging a coincidence between bits of the n-bit image data and corresponding bits of the n-bit count data, the coincidence circuit including, a plurality of single value detecting circuits for detecting that corresponding bits of the n-bit image data and the n-bit count data have a predetermined value, and a first coincidence judging circuit for determining a coincidence between the n-bit image data and the n-bit count data by detecting a first time that said single value detecting circuits corresponding to all bits of said n-bit image data having said predetermined value have detected that said corresponding bits of said n-bit image data and said n-bit count data have said predetermined value during an up-counting of said counter; and a switching circuit for controlling the supply of current to said resistors in accordance with a count signal of said counter at a time when said first coincidence judging circuit determines that all of said single bit detecting circuits have detected that said corresponding bits of said n-bit image data and said n-bit count data have said predetermined value.
Claim 2
Dependent Claim
223 words
A current control circuit for controlling the supply of current to a plurality of resistors for use in a thermal print head in a printing of an image corresponding to n-bit image data comprising: a counter for producing n-bit count data; a coincidence circuit for judging a coincidence between bits of the n-bit image data and corresponding bits of the n-bit count data, the coincidence circuit including, a plurality of single value detecting circuits for detecting that corresponding bits of the n-bit image data and the n-bit count data have a predetermined value, and a first coincidence judging circuit for determining a coincidence between the n-bit image data and the n-bit count data by detecting a first time that said single value detecting circuits corresponding to all bits of said n-bit image data having said predetermined value have detected that said corresponding bits of said n-bit image data and said n-bit count data have said predetermined value during an up-counting of said counter; and a switching circuit for controlling the supply of current to said resistors in accordance with a count signal of said counter at a time when said first coincidence judging circuit determines that all of said single bit detecting circuits have detected that said corresponding bits of said n-bit image data and said n-bit count data have said predetermined value.
Claim 3
Dependent Claim
76 words
The current control circuit according to claim 1, wherein said plurality of single value detecting circuits comprise: a plurality of shift registers for receiving said n-bit image data, said shift registers having n stages, each of said stages storing a different one of the bits of the n-bit image data; and a plurality of latches connected to corresponding ones of said shift registers for receiving the bits of the n-bit image data stored in said stages.
Claim 4
Dependent Claim
81 words
The current control circuit according to claim 2, wherein said first coincidence judging circuit comprises a plurality of comparators, each of said comparators being associated with and connected to a different one of said plurality of latches to receive said bits of said image data stored in said stages of said associated latch, each of said comparators being further connected to said counter for comparing said bits of said n-bit image data to said corresponding bits of the n-bit count data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |