Programmable ripple counter having exclusive OR gates

Claim 2

A counter circuit, comprising: first register means for storing a predetermined number representing a quantity of pulses to be counted, means for counting a series of pulses received therein from an external source, said counting means including second means for storing the counted pulses, the second storing means including means responsive to a reference timing signal received from another external source for resetting the second storing means to an initial count, said counting means including means for asynchronously coupling in series elements of the second storing means to propogate the count therethrough, the coupling means being coupled to the first mentioned storing means so as to receive the predetermined number from the first mentioned storing means, the coupling means generating a logical combination of the predetermined number and the instantaneous count stored in the second storing means, said second storing means storing a terminal count when the predetermined quantity of pulses has been counted; and means coupled to said counting means for decoding the terminal count, said decoding means including means for generating a terminal count signal for use by an external device.

Claim 3

A counter circuit, comprising: first means for generating pulses in series to be counted; second means for generating a reference timing signal; register means for storing a predetermined number representing a quantity of the pulses to be counted; means coupled in series to said first generating means for counting the pulses, said counting means including second means for storing the counted pulses, the second storing means including means responsive to the reference timing signal for resetting the second storing means to an initial count, said counting means including means for asynchronously coupling elements of the second storing means in series to propogate the count therethrough, the coupling means being coupled in parallel to said register means and receiving the predetermined number, the coupling means generating a non-equivalence of the predetermined number and the instantaneous count stored in the second storing means, said counting means storing a terminal count when the predetermined quantity of pulses has been counted; means coupled to said counting means for decoding the terminal count; and means for utilizing a terminal count signal generated by said decoding means.

Claim 4

A counter circuit, comprising: first means for generating pulses in series to be counted; second means for generating a reference timing signal; register means for storing a predetermined number representing a quantity of the pulses to be counted; means coupled in series to said first generating means for counting the pulses, said counting means including second means for storing the counted pulses, the second storing means including means responsive to the reference timing signal for resetting the second storing means to an initial count, said counting means including means for asynchronously coupling elements of the second storing means in series to propogate the count therethrough, the coupling means being coupled in parallel to said register means and receiving the predetermined number, the coupling means generating a non-equivalence of the predetermined number and the instantaneous count stored in the second storing means, said counting means storing a terminal count when the predetermined quantity of pulses has been counted; means coupled to said counting means for decoding the terminal count; and means for utilizing a terminal count signal generated by said decoding means.

Claim 5

The counter circuit of claim 2, wherein said first generating means comprises a trigger-signal generator circuit of a display device.

Claim 6

The counter circuit of claim 2, wherein said second generating means comprises a first sweep-gating circuit of a display device.

Claim 7

The counter circuit of claim 2, wherein said utilizing means comprises a second sweep-gating circuit of a display device.

Claim 8

The counter circuit of claim 5, wherein said second generating means comprises a first sweep-gating circuit of the display device.

Claim 9

The counter circuit of claim 6, wherein said first generating means comprises a trigger-signal generator circuit of the display device.

Claim 10

A programmable ripple counter, comprising: first means for generating pulses to be counted; first means for storing a predetermined number representing a quantity of the pulses to be counted; means receiving in series the pulses for counting the pulses, said counting means including at least two bistable means for storing the number of pulses counted and exclusive OR logic means for asynchronously coupling the bistable storing means in series, the exclusive OR logic means receiving in parallel from said first storing means the predetermined number representing the quantity of pulses to be counted; means coupled to said counting means for detecting a terminal count of said counting means, said detecting means including second means for generating a terminal count signal, the terminal count signal occurring when said counting means has counted the predetermined number of pulses; and means for utilizing the terminal count signal.

Claim 11

A programmable ripple counter, comprising: first means for generating pulses to be counted; first means for storing a predetermined number representing a quantity of the pulses to be counted; means receiving in series the pulses for counting the pulses, said counting means including at least two bistable means for storing the number of pulses counted and exclusive OR logic means for asynchronously coupling the bistable storing means in series, the exclusive OR logic means receiving in parallel from said first storing means the predetermined number representing the quantity of pulses to be counted; means coupled to said counting means for detecting a terminal count of said counting means, said detecting means including second means for generating a terminal count signal, the terminal count signal occurring when said counting means has counted the predetermined number of pulses; and means for utilizing the terminal count signal.

Claim 12

The programmable ripple counter of claim 8, wherein said first generating means comprises a trigger-signal generator of a display device.

Claim 13

The programmable ripple counter of claim 8, wherein said utilizing means comprises a sweep-gating circuit of a display device.

Claim 14

The programmable ripple counter of claim 10, wherein said first generating means comprises a trigger-signal generator of the display device.

Claim 15

A programmable ripple counter, comprising: a source of reference timing signals; a source of pulses in series to be counted; a register storing a predetermined number representing a quantity of the pulses to be counted; a counter coupled to said register, said counter having an input stage receiving the pulses to be counted, a final stage, and intermediate stages in series with the input and final stages according to a maximum number of pulses to be counted, each of the stages including a bistable element having a trigger input, and an output, each of the stages being asynchronously coupled to an adjacent stage in the series through an exclusive OR element having a first input connected to the output of the bistable element, a second input receiving a signal representing one digit of the predetermined number, and an output, the output of the exclusive OR elements of the input and intermediate stages being connected to the trigger input of the bistable element of a succeeding one of the stages of the series, each of the bistable elements receving the reference timing signal and being reset upon occurrence thereof to initiate counting the pulses, said counter reaching a terminal count when the predetermined quantity of pulses has been counted; and a decode logic element coupled to said counter, said decode logic element generating an output signal when said counter reaches the terminal count.

Claim 16

A programmable ripple counter, comprising: a source of reference timing signals; a source of pulses in series to be counted; a register storing a predetermined number representing a quantity of the pulses to be counted; a counter coupled to said register, said counter having an input stage receiving the pulses to be counted, a final stage, and intermediate stages in series with the input and final stages according to a maximum number of pulses to be counted, each of the stages including a bistable element having a trigger input, and an output, each of the stages being asynchronously coupled to an adjacent stage in the series through an exclusive OR element having a first input connected to the output of the bistable element, a second input receiving a signal representing one digit of the predetermined number, and an output, the output of the exclusive OR elements of the input and intermediate stages being connected to the trigger input of the bistable element of a succeeding one of the stages of the series, each of the bistable elements receving the reference timing signal and being reset upon occurrence thereof to initiate counting the pulses, said counter reaching a terminal count when the predetermined quantity of pulses has been counted; and a decode logic element coupled to said counter, said decode logic element generating an output signal when said counter reaches the terminal count.

Claim 17

The programmable ripple counter of claim 12, wherein said source of pulses comprises a trigger-signal generator circuit of a display device.

Claim 18

The programmable ripple counter of claim 12, wherein the predetermined count is a maximum count of the counter.

Claim 19

A programmable counter circuit, comprising: means for storing a data item representing a number of pulses to be counted; PG,16 a counter having a plurality of stages; means disposed between said counter stages for asynchronously coupling said counter stages in cascade relation, said coupling means comprising gating means each receiving an output from one of the plurality of stages for propagating a count through said counter, said gating means including means receiving an output from said storing means for providing a presetting input of a counter stage; and means coupled to said counter for detecting a predetermined terminal count of said counter.

Claim 20

A programmable counter circuit, comprising: means for storing a data item representing a number of pulses to be counted; PG,16 a counter having a plurality of stages; means disposed between said counter stages for asynchronously coupling said counter stages in cascade relation, said coupling means comprising gating means each receiving an output from one of the plurality of stages for propagating a count through said counter, said gating means including means receiving an output from said storing means for providing a presetting input of a counter stage; and means coupled to said counter for detecting a predetermined terminal count of said counter.

Claim 21

The counter circuit of claim 14, wherein each said gating means comprises an exclusive OR logic element.