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US4392065A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic circuit for eliminating chatter

Assignee: Honeywell Inc
•
Filing: 1981-06-18
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Granted: 1983-07-05
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Expires: 2001-06-18
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Abstract

Abstract An electronic circuit for eliminating chatter in an output circuit due to contact bounce of switches connected to an input circuit. The electronic circuit has a first and second group of D-flip-flop gates which have outputs for providing a signal to a third group of D-flip-flop gates when triggered by a clock signal when the inputs switch contact bounce has terminated.

Inventors

  • 👤 Ralph E. Stiglich

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 02:28
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H03K5/01

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 483 words
An electronic circuit for eliminating from at least two input switches the effect of contact bounce, comprising a first group of a first and a second switch means each having two input circuits and one output circuit whereby upon an identical input signal appearing on said two input circuits an output signal exists on said output circuit, first circuit means connecting each of the two input switches providing an input signal to one of said two input circuits of said first and second switch means, a source of timing pulses connected to the other of said two input circuits of said first and second switch means, a second group of a third and fourth switch means each having two input circuits and one output circuit whereby upon an identical input signal appearing on said two input circuits an output signal exists on said output circuit, second circuit means connecting each of said one output circuits of said first and second switch means to one of said input circuits of said third and fourth switch means, third circuit means connecting said source of timing pulses to a second of said two input circuits of said third and fourth switch means, fifth and sixth switch means having two input circuits and an output circuit whereby upon an input signal appearing on each of said two input circuits an output signal exists on said output circuit, fourth circuit means connecting said output circuit of said first and third switch means to one of said input circuits of said fifth switch means and said output circuit of said second and fourth switch means to said input circuits of said sixth switch means, a seventh switch means having at least three input circuits and an output circuit whereby upon identical input signals appearing on all three input circuits, an output signal exists on said output circuit, fifth circuit means connecting said output circuits of each of said fifth and sixth switch means to a first and second input circuits of said seventh switch means and said source of timing pulses to a third input circuit of said seventh switch means, a third group of an eighth and ninth switch means each having two input circuits and an output circuit, whereby upon an identical input signal appearing on each of said two input circuits an output signal exists on said output circuit, and means connecting said output of each of said third and fourth switch means to one of said input circuits of said eighth and ninth switch means respectively and said output circuit of said seventh switch means to each of the other input circuits of said eighth and ninth switch means to provide an output signal at said output circuits of said eighth and ninth switch means indicative of the input signal of the input switches after the contact bounce of the two input switches has terminated.
Claim 2
Dependent Claim 483 words
An electronic circuit for eliminating from at least two input switches the effect of contact bounce, comprising a first group of a first and a second switch means each having two input circuits and one output circuit whereby upon an identical input signal appearing on said two input circuits an output signal exists on said output circuit, first circuit means connecting each of the two input switches providing an input signal to one of said two input circuits of said first and second switch means, a source of timing pulses connected to the other of said two input circuits of said first and second switch means, a second group of a third and fourth switch means each having two input circuits and one output circuit whereby upon an identical input signal appearing on said two input circuits an output signal exists on said output circuit, second circuit means connecting each of said one output circuits of said first and second switch means to one of said input circuits of said third and fourth switch means, third circuit means connecting said source of timing pulses to a second of said two input circuits of said third and fourth switch means, fifth and sixth switch means having two input circuits and an output circuit whereby upon an input signal appearing on each of said two input circuits an output signal exists on said output circuit, fourth circuit means connecting said output circuit of said first and third switch means to one of said input circuits of said fifth switch means and said output circuit of said second and fourth switch means to said input circuits of said sixth switch means, a seventh switch means having at least three input circuits and an output circuit whereby upon identical input signals appearing on all three input circuits, an output signal exists on said output circuit, fifth circuit means connecting said output circuits of each of said fifth and sixth switch means to a first and second input circuits of said seventh switch means and said source of timing pulses to a third input circuit of said seventh switch means, a third group of an eighth and ninth switch means each having two input circuits and an output circuit, whereby upon an identical input signal appearing on each of said two input circuits an output signal exists on said output circuit, and means connecting said output of each of said third and fourth switch means to one of said input circuits of said eighth and ninth switch means respectively and said output circuit of said seventh switch means to each of the other input circuits of said eighth and ninth switch means to provide an output signal at said output circuits of said eighth and ninth switch means indicative of the input signal of the input switches after the contact bounce of the two input switches has terminated.
Claim 3
Dependent Claim 77 words
The invention of claim 1 wherein said first and second switch means are flip-flop gates having a reset input circuit, said output signal on said output circuits doesn't change until one of said input signals is removed and a reset signal applied to said reset input circuit restores said gates to a standby operating condition, said third switch means is an exclusive NOR gate, and said clock pulse source means provides a pulsing voltage of 64 Hz.
Claim 4
Dependent Claim 60 words
The invention of claim 1 wherein said first, second, third, fourth, eighth and ninth switch means are D-flip-flop gates each having a reset signal input to which a reset signal source can be selectively connected to restore said gates to a normal state after said output signal of said output circuits of said eighth and ninth gates has been used.
Claim 5
Dependent Claim 25 words
The invention of claim 3 wherein said fifth and sixth switch means are exclusive NOR gates, and said seventh switch means is a NAND gate.
Claim 6
Dependent Claim 21 words
The invention of claim 4 wherein said source of clock pules is a cyclic voltage source of a 64 Hz frequency.
Claim 7
Dependent Claim 36 words
The invention of claim 5 wherein said input switches provide a binary input to said first and second gates whereby a similar binary output is provided on said output circuits of said eighth and ninth gates.
Claim 8
Dependent Claim 35 words
The invention of claim 5 wherein a time delay before said output signal is provided at said output circuits ranges between 24 to 40 milliseconds for 64 Hz pulses from said source of clock pulses.
Claim 9
Dependent Claim 45 words
The invention of claim 1 wherein each of said first, second and third groups of switch means has at least three switch means for providing a circuit to delay said output until the signal from a three binary coded input is free of contact bounce.
Claim 10
Dependent Claim 29 words
The invention of claim 8 wherein all of said switch means of each of said groups are connected to a reset signal source and said source of clock pulses.
Claim 11
Dependent Claim 35 words
The invention of claim 4, comprising inverter means connected to saidf output of said NAND gate, to provide an output from each side of said inverter means to said switch means of said third group.

References Cited (Backward Citations)

US3989960A Cited
US4057738A Cited
US4073131A Cited
US4198579A Cited
US4185210A Cited
US4159497A Cited
US4281259A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-07-04 1987-01-03 1987-07-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-07-04 1991-01-03 1991-07-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-07-04 1995-01-03 1995-07-05 $7700.00 Window Closed / Lapsed

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