Time-setting and displaying mode control circuit for an electronic timepiece

Claim 2

A time-setting and displaying mode control circuit for an electronic timepiece comprising a first and a second switch, a first-switch operative condition detecting circuit for generating a signal upon operation of said first switch, a second-switch operative condition detecting circuit for generating a signal upon operation of said second switch, a first ring counter having a first shift register circuit composed of cascade connected shift registers and a first logic circuit whose input terminals are connected to output terminals of said shift registers, respectively, and whose output terminal is connected to the input terminal of the first stage shift register of said first shift register circuit, and adapted to generate a signal corresponding to one of time-setting modes from output terminals of said shift registers of said first shift register circuit, a second ring counter including a second shift register circuit having at least one shift register, a second logic circuit having input terminals connected to said output terminal of said first logic circuit, an input terminal of said second shift register circuit, and an output terminal of said at least one shift register of said second shift register circuit, and controlled by an output signal from said first logic circuit to generate a signal corresponding to one of time-displaying modes, a first mode control circuit connected to said first-switch operative condition detecting circuit and adapted to shift, upon operation of said first switch under a time-setting mode, the content of said first ring counter and to change-over, upon operation of said first switch under either one of first and second specified time displaying modes, said time displaying mode to a corresponding one of first and second specified time setting modes by setting a specified shift register of said first shift register circuit, and a second mode control circuit connected to said second-switch operative condition detecting circuit and said first logic circuit and adapted to generate an output signal to shift the content of said second ring counter each time said second switch is operated during a time-displaying mode period.

Claim 3

A time-setting and displaying mode control circuit according to claim 1, wherein said second logic circuit includes a plurality of AND circuits each having a first input terminal connected to said output terminal of said first logic circuit and a second input terminal connected to an input terminal of said second shift register circuit and the output terminal of said at least one shift register of said second shift register circuit; and said first mode control circuit includes AND circuits having first input terminals connected to an output terminal of said first-switch operative condition detecting circuit, second input terminals respectively connected to output terminals of specified two AND circuits of said second logic circuit for receiving an output signal from said second ring counter and output terminals respectively connected to set terminals of specified two shift registers of said first shift register circuit, and an AND circuit adapted to receive a logical sum signal of output signals from all of said shift registers of said first shift register circuit and an output signal from said first-switch operative condition detecting circuit and having an output terminal connected to a clock terminal of each shift register of said first shift register circuit.

Claim 4

A time-setting and displaying mode control circuit according to claim 2, wherein said second ring counter is composed of one shift register and an inverter for inverting an output signal of the shift register to supply an output signal to an input terminal of said shift register.

Claim 5

A time-setting and displaying mode control circuit according to claim 2, wherein said second ring counter is composed of cascade connected shift registers and a NOR circuit having input terminals respectively connected to output terminals of said cascade connected shift registers of said second ring counter and an output terminal connected to an input terminal of an initial stage shift register of said cascade connected shift register of said second ring counter.

Claim 6

A time-setting and displaying mode control circuit according to claim 2, which further comprises a reset circuit coupled to said first switch to generate an output signal during a period by which the length of time of depressing said first switch exceeds a specified value, thereby to reset each shift register of said first shift register circuit.

Claim 7

A time-setting and displaying mode control circuit according to claim 1, which further comprises a reset circuit coupled to said first switch to generate an output signal during a period by which the length of time of depressing said first switch exceeds a specified value, thereby to reset each shift register of said first shift register circuit.

Claim 8

A time-setting and displaying mode control circuit according to claim 1, which further comprises a pulse generator connected to said second switch to generate a pulse signal during a period by which the length of time of depressing said second switch exceeds a specified value, and AND circuits having first input terminals connected to said output terminals of said shift registers of said first shift register circuit, respectively, and second input terminals connected to an output terminal of said pulse generator.

Claim 9

A time-setting and displaying mode control circuit according to claim 1, wherein said second mode control circuit is composed of an AND circuit having an output terminal connected to a clock terminal of said at least one shift register of said second shift register circuit.

Claim 10

A time-setting and displaying mode control circuit according to claim 1, wherein said first logic circuit is composed of a NOR circuit.

Claim 11

A time-setting and displaying mode control circuit according to claim 1, wherein said first-switch operative condition detecting circuit includes three cascade connected shift registers an input terminal of the first stage shift register of which is connected to said first switch, and a first NOR gate for receiving a signal prepared by inverting an output signal from the second stage shift register of said three cascade connected shift registers and an output signal from the final stage shift register of said three cascade connected shift registers; said first mode control circuit has five AND gates having, respectively, first input terminals connected to an output terminal of said first NOR gate; said first shift register circuit of said first ring counter is composed of four shift registers; said first logic circuit is composed of a second NOR gate; said second-switch operative condition detecting circuit includes three cascade connected shift registers an input terminal of the first stage shift register of which is connected to said second switch, and a third NOR gate for receiving a signal prepared by inverting an output signal from the second stage shift register of said three cascade connected shift registers of said second-switch operative condition detecting circuit and an output signal from the final stage shift register of said three cascade connected shift registers of said second-switch operative condition detecting circuit; said second ring counter includes two cascade connected shift registers and a fourth NOR gate having an input terminal connected to respective output terminals of said two cascade connected shift registers and an output terminal connected to an input terminal of said second shift register circuit; said second logic circuit is composed of three AND gates having respectively first input terminals connected to output terminals of said second shift register circuit and said output terminal of said fourth NOR gate and second input terminals connected to an output terminals of said second NOR gate; said second mode control circuit is composed of an AND gate having input terminsls respectively connected to the output terminals of said second and third NOR gates and an output terminal connected to clock terminals of the shift registers of said second shift register circuit; said output terminal of said second NOR gate is connected to a second input terminal of a first one of said five AND gates of said first mode control circuit through an inverter, an output terminal of said first one of said five AND gates being connected to clock terminals of the shift registers of said first shift register circuit; an output terminal of that first AND gate of said second logic circuit which receives an output signal from said fourth NOR gate is connected to a second input terminal of a second one of said five AND gates of said first mode control circuit, an output terminal of said second one of said five AND gates being connected to a set terminal of the first stage shift register of said second shift register circuit; an output terminal of a second AND gate of said second logic circuit is connected to a second input terminal of a third one of said five AND gates of said first mode control circuit, an output terminal of said third of said five AND gates being connected to a set terminal of the third stage shift register of said first shift register circuit; an output terminal of a third AND gate of said second logic circuit is connected to a second input terminal of a fourth one of said five AND gates of said first mode control circuit, said fourth one of said five AND gates being adapted to generate a "second" resetting signal when enabled; and an output terminal of a final stage shift register of said first shift register circuit is connected to a second input terminal of a fifth one of said five AND gates of said first mode control circuit, said fifth one of said AND gates being adapted to reset each of said shift registers of said second shift register circuit when enabled.

Claim 12

A time-setting and displaying mode control circuit according to claim 10, which further comprises a reset circuit including an first stage shift register having an input terminal connected to an output terminal of the second stage shift register of said first-switch operative condition detecting circuit, a second stage shift register cascade connected to said first stage shift register of said reset circuit, and an AND gate having input terminals respectively connected to respective output terminals of said first and second stage shift registers of said reset circuit and an output terminal connected to a reset terminal of each shift register of said first shift register circuit, whereby to generate an output signal during a period by which the length of time of depressing said first switch exceeds a specified value to reset each shift register of said first shift register circuit.

Claim 13

A time-setting and displaying mode control circuit according to claim 10, which further comprises a pulse generator having an first stage shift register connected to an output terminal of a second stage shift register of said second-switch operative condition detecting circuit, a second stage shift register cascade connected to said initial stage shift register of said pulse generator, a sixth AND gate having input terminals respectively connected to output terminals of said first and second stage shift registers of said pulse generator, a seventh AND gate for receiving an output signal from said sixth AND gate and a pulse signal having a specified frequency, and a fifth NOR gate for receiving respective output signals from said seventh AND gate and said third NOR gate of said second-switch operative condition detecting circuit, whereby to generate a pulse signal having said specified frequency during a period by which the length of time of depressing said second switch exceeds a specified value; a sixth NOR gate for receiving respective output signals from said pulse generator and said second NOR gate; and four AND gates having respectively first input terminals connected to an output terminal of said sixth NOR gate and second input terminals connected to the output terminals of said shift registers of said first shift register circuit.

Claim 14

A time-setting and displaying mode control circuit according to claim 5 in which said reset circuit comprises two serially connected shift registers and an AND gate whose input terminals are connected to the output terminals of said two serially connected shift registers, respectively, and whose output terminal is connected to the reset terminal of each shift register of said first shift register circuit, wherein the input terminal of the first stage of said two serially connected shift registers is coupled to said first switch and said AND gate produces an output signal when said first switch is kept depressed longer than a specified period of time.