US4396909A
Expired / Lapsed
US
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Frequency generating circuit
Assignee: Casio Computer Co Ltd
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Filing: 1981-05-28
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Granted: 1983-08-02
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Expires: 2001-05-28
Abstract
Abstract A frequency generating circuit comprises a piezoelectric buzzer (18) which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit (1) made up of a multi-stage flip-flop array for frequency dividing a reference frequency signal; logic setting means (3 1 to 3 6 , 4) which is responsive to a plurality of externally generated setting signals (C 1 to C 6 ) to effect a logic setting for obtaining the desired frequency; control means (5, 6, 7, 10, 11, 12) for outputting a control signal to reset terminals of the flip-flops on the basis of an output signal of the logic setting means for resetting the frequency dividing circuit to obtain the desired frequency; pulse width setting means (15) coupled to output terminals of at least two predetermined flip-flop stages of the frequency dividing circuit to set the pulse width of a driving signal to the desired pulse width; and driving signal generating means (8, 13, 14, 16) for delivering a driving signal to the piezoelectric buzzer (18) as a function of the control signal of the control means and the output signal of the pulse width setting means, the driving signal having the desired frequency and the desired pulse width.
Inventors
- 👤 Kazuyasu Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; G; G10; G10H; G10H5/00; G10H5/02; G10H5/06; H03K17/00; H03K17/28; H03K17/51; H03K17/56; H03K17/60; H03K17/64; H03K23/00; H03K23/64; H03K23/66; H03K5/156; H03K7/00; H03K7/08
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
242 words
A frequency generating circuit comprising: a piezoelectric buzzer which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit comprised of a multi-stage flip-flop array for frequency dividing a reference frequency signal, said flip-flop stages of said frequency dividing circuit having reset terminals and output terminals; logic setting means coupled to said frequency dividing circuit and including means responsive to a plurality of externally generated setting signals to effect a logic setting for obtaining said desired frequency; control means coupled to an output of said logic setting means and to said reset terminals of said frequency dividing circuit for outputting a control signal to said reset terminals on the basis of an output signal of said logic setting means, said frequency dividing circuit being reset by said control signal applied to said reset terminals to obtain said desired frequency; pulse width setting means coupled to said output terminals of at least two predetermined flip-flop stages of said frequency dividing circuit to set the pulse width of a driving signal to said desired pulse width; and driving signal generating means coupled to said control means and to said pulse width setting means for delivering a driving signal to said piezoelectric buzzer as a function of said control signal of said control means and the output signal of said pulse width setting means, said driving signal having said desired frequency and said desired pulse width.
Claim 2
Dependent Claim
242 words
A frequency generating circuit comprising: a piezoelectric buzzer which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit comprised of a multi-stage flip-flop array for frequency dividing a reference frequency signal, said flip-flop stages of said frequency dividing circuit having reset terminals and output terminals; logic setting means coupled to said frequency dividing circuit and including means responsive to a plurality of externally generated setting signals to effect a logic setting for obtaining said desired frequency; control means coupled to an output of said logic setting means and to said reset terminals of said frequency dividing circuit for outputting a control signal to said reset terminals on the basis of an output signal of said logic setting means, said frequency dividing circuit being reset by said control signal applied to said reset terminals to obtain said desired frequency; pulse width setting means coupled to said output terminals of at least two predetermined flip-flop stages of said frequency dividing circuit to set the pulse width of a driving signal to said desired pulse width; and driving signal generating means coupled to said control means and to said pulse width setting means for delivering a driving signal to said piezoelectric buzzer as a function of said control signal of said control means and the output signal of said pulse width setting means, said driving signal having said desired frequency and said desired pulse width.
Claim 3
Dependent Claim
106 words
The frequency generating circuit of claim 1, wherein: said logic setting means comprises a plurality of OR gates and one AND gate coupled to the outputs of said OR gates, the number of said OR gates corresponding to the number of said flip-flop stages of said frequency dividing circuit, and outputs of said flip-flop stages being respectively coupled to one of said OR gates; an output signal of the respective stage flip-flops of said frequency dividing circuit and the respective externally generated setting signals being ORed by a respective OR gate, the output signals of the respective OR gates being ANDed by said one AND gate.
Claim 4
Dependent Claim
134 words
The frequency generating circuit of claim 1, wherein: said control means comprises a NOR gate, a first inverter, a second inverter, a first capacitor and a second capacitor; an input of said NOR gate being coupled to said output of said logic setting means, the output of said NOR gate being coupled to the input of said first inverter, said first capacitor being coupled between the output of said NOR gate and ground potential, the output of said first inverter being coupled to the input of said second inverter, said second capacitor being coupled between the output of said first inverter and ground potential, and the output of said second inverter being coupled to supply said control signal to said driving signal generating means and to said reset terminals of said frequency dividing circuit.
Claim 5
Dependent Claim
140 words
The frequency generating circuit of claim 2, wherein: said control means comprises a NOR gate, a first inverter, a second inverter, a first capacitor and a second capacitor; an input of said NOR gate being coupled to said output of said one AND gate of said logic setting means, the output of said NOR gate being coupled to the input of said first inverter, said first capacitor being coupled between the output of said NOR gate and said ground potential, the output of said first inverter being coupled to the input of said second inverter, said second capacitor being coupled between the output of said first inverter and ground potential, and the output of said second inverter being coupled to supply said control signal to said driving signal generating means and to said reset terminals of said frequency dividing circuit.
Claim 6
Dependent Claim
146 words
The frequency generating circuit of claim 1, wherein: said driving signal generating means includes a first flip-flop, a second flip-flop coupled to an output of said first flip-flop, and a comparison circuit coupled to an output of both said first and second flip-flops; said first flip-flop being coupled to receive said output signal of said control means so as to be set or reset by said output signal of said control means; and an output signal of said first flip-flop being coupled directly to said comparison circuit, and an output of said first flip-flop being coupled to said comparison circuit through said second flip-flop subjected to a read-in control by an output signal of said pulse width setting means, said comparison circuit comparing the output signals of said first and second flip-flops with each other, the output of said comparison circuit corresponding to said driving signal.
Claim 7
Dependent Claim
32 words
The frequency generating circuit of claim 5, wherein said driving signal generating means comprises means responsive to the output of said comparison circuit for supplying said driving signal to said piezoelectric buzzer.
Claim 8
Dependent Claim
146 words
The frequency generating circuit of claim 2, wherein: said driving signal generating means includes a first flip-flop, a second flip-flop coupled to an output of said first flip-flop, and a comparison circuit coupled to an output of both said first and second flip-flops; said first flip-flop being coupled to receive said output signal of said control means so as to be set or reset by said output signal of said control means; and an output signal of said first flip-flop being coupled directly to said comparison circuit, and an output of said first flip-flop being coupled to said comparison circuit through said second flip-flop subjected to a read-in control by an output signal of said pulse width setting means, said comparison circuit comparing the output signals of said first and second flip-flops with each other, the output of said comparison circuit corresponding to said driving signal.
Claim 9
Dependent Claim
32 words
The frequency generating circuit of claim 7, wherein said driving signal generating means comprises means responsive to the output of said comparison circuit for supplying said driving signal to said piezoelectric buzzer.
Claim 10
Dependent Claim
146 words
The frequency generating circuit of claim 3, wherein: said driving signal generating means includes a first flip-flop, a second flip-flop coupled to an output of said first flip-flop, and a comparison circuit coupled to an output of both said first and second flip-flops; said first flip-flop being coupled to receive said output signal of said control means so as to be set or reset by said output signal of said control means; and an output signal of said first flip-flop being coupled directly to said comparison circuit, and an output of said first flip-flop being coupled to said comparison circuit through said second flip-flop subjected to a read-in control by an output signal of said pulse width setting means, said comparison circuit comparing the output signals of said first and second flip-flops with each other, the output of said comparison circuit corresponding to said driving signal.
Claim 11
Dependent Claim
32 words
The frequency generating circuit of claim 9, wherein said driving signal generating means comprises means responsive to the output of said comparison circuit for supplying said driving signal to said piezoelectric buzzer.
Claim 12
Dependent Claim
146 words
The frequency generating circuit of claim 4, wherein: said driving signal generating means includes a first flip-flop, a second flip-flop coupled to an output of said first flip-flop, and a comparison circuit coupled to an output of both said first and second flip-flops; said first flip-flop being coupled to receive said output signal of said control means so as to be set or reset by said output signal of said control means; and an output signal of said first flip-flop being coupled directly to said comparison circuit, and an output of said first flip-flop being coupled to said comparison circuit through said second flip-flop subjected to a read-in control by an output signal of said pulse width setting means, said comparison circuit comparing the output signals of said first and second flip-flops with each other, the output of said comparison circuit corresponding to said driving signal.
Claim 13
Dependent Claim
32 words
The frequency generating circuit of claim 11, wherein said driving signal generating means comprises means responsive to the output of said comparison circuit for supplying said driving signal to said piezoelectric buzzer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |