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US4988892A
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Method and circuit for generating dependent clock signals
Assignee: ATARI Corp
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Filing: 1989-06-02
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Granted: 1991-01-29
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Expires: 2009-06-02
Abstract
Abstract A method and circuit generate a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal and inverting it to create a second master clock signal that is one hundred eighty degrees out of phase with the first master clock signal. The second master clock signal is used to drive a flip flop type circuit so that the flip flop circuit changes states when the first master clock signal is at a "zero" level and the second master clock signal is at a "one " level. The output of the flip flop circuit is enabled using the first master clock signal. Connected to the output of the tri-state driver is a repeater circuit of the type having an output that remains the same as the input until the input level is changed. The resulting dependent clock signal has a minimal skew with respect to the first master clock signal because the output of the flip flop circuit has become stable by the time the tri-state driver is enabled by the first master clock signal. Thus, the skew line is limited to the delay time of the tri-state driver.
Inventors
- 👤 David L. Needle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:00
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/00006; H03K5/156
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
278 words
A circuit for generating a dependent clock signal from a master clock signal with a minimal skew of the dependent clock signal - with respect to the master clock signal, which comprises: a source of the master clock signal, an inverter having an input line and an output line, the input line being connected to said source of the master clock signal, means for generating a dependent clock signal, having a clocking input line and an output line, the clocking input line being connected to the output of the inverter, a tri-state driver having an input line, an enable line and an output line, the output line being capable of producing a low voltage state, a high voltage state and a high impedence state, the input line of the tri-state driver being connected to the output line of the means for generating a dependent clock signal and the enable line being connected to the master clock signal, and a repeater circuit having an input line and an output line, wherein the input line and the output line of the repeater circuit is connected to the output line of the tri-state driver, wherein said circuit generates a dependent clock signal with minimal skew by driving the means for generating dependent signal with the output of the inverter and enabling the tri-state buffer with the master clock signal; the output line of the means for generating a dependent clock signal being stable by the time the enable line of the tri-state buffer is activated by the master clock signal, thereby reducing the skew between the master clock signal and the dependent clock signal to the delay of the tri-state driver.
Claim 2
Dependent Claim
278 words
A circuit for generating a dependent clock signal from a master clock signal with a minimal skew of the dependent clock signal - with respect to the master clock signal, which comprises: a source of the master clock signal, an inverter having an input line and an output line, the input line being connected to said source of the master clock signal, means for generating a dependent clock signal, having a clocking input line and an output line, the clocking input line being connected to the output of the inverter, a tri-state driver having an input line, an enable line and an output line, the output line being capable of producing a low voltage state, a high voltage state and a high impedence state, the input line of the tri-state driver being connected to the output line of the means for generating a dependent clock signal and the enable line being connected to the master clock signal, and a repeater circuit having an input line and an output line, wherein the input line and the output line of the repeater circuit is connected to the output line of the tri-state driver, wherein said circuit generates a dependent clock signal with minimal skew by driving the means for generating dependent signal with the output of the inverter and enabling the tri-state buffer with the master clock signal; the output line of the means for generating a dependent clock signal being stable by the time the enable line of the tri-state buffer is activated by the master clock signal, thereby reducing the skew between the master clock signal and the dependent clock signal to the delay of the tri-state driver.
Claim 3
Dependent Claim
38 words
A circuit is defined in claim 1, wherein the means for generating a dependent signal comprises a D-type flip flop having a D input, and a Q' output, wherein the D input is connected to the Q' output.
Claim 4
Dependent Claim
26 words
A circuit as defined in claim 2, wherein the input line of the tri-state driver is connected to the Q' output of the D-type flip flop.
Claim 5
Dependent Claim
42 words
A circuit as defined in claim 1, wherein the repeater circuit comprises a driver having an input and an output line, wherein the input line of the repeater circuit is connected to the output line of the repeater circuit through a resistor.
Claim 6
Independent Claim
221 words
A method of generating a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal, which comprises: providing a first master clock signal which alternates between a "zero" level and a "one" level, inverting the first master clock signal to create a second master clock signal that is 180 degrees out of phase with respect to the first master clock signal, driving a flip flop circuit with the second master clock signal, wherein the flip flop circuit is of the type having an output that can remain in either a "one" state or a "zero" state, the output of the flip flop changing states when the second master clock signal changes from a zero level to a one level, enabling a tri-state driver, with the first master clock signal, wherein the tri-state driver is of the type having an input coupled the output of the flip flop circuit and an output that can remain in either a low state, a high state or a high impedance state, and connecting to the output of the tri-state driver a repeater circuit of the type having an input level and an output level such that the output level remains the same as the input level until the input level is changed.
Claim 7
Independent Claim
221 words
A method of generating a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal, which comprises: providing a first master clock signal which alternates between a "zero" level and a "one" level, inverting the first master clock signal to create a second master clock signal that is 180 degrees out of phase with respect to the first master clock signal, driving a flip flop circuit with the second master clock signal, wherein the flip flop circuit is of the type having an output that can remain in either a "one" state or a "zero" state, the output of the flip flop changing states when the second master clock signal changes from a zero level to a one level, enabling a tri-state driver, with the first master clock signal, wherein the tri-state driver is of the type having an input coupled the output of the flip flop circuit and an output that can remain in either a low state, a high state or a high impedance state, and connecting to the output of the tri-state driver a repeater circuit of the type having an input level and an output level such that the output level remains the same as the input level until the input level is changed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |