US4115706A
Expired / Lapsed
US
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Integrated circuit having one-input terminal with selectively varying input levels
Assignee: Toshiba Corp
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Filing: 1977-05-31
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Granted: 1978-09-19
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Expires: 1997-05-31
Abstract
Abstract An integrated circuit includes an input terminal to which a "1," "float" and "0" level input signals are selectively supplied; a clock pulse generator for generating a second clock pulse during the high level period of a first clock pulse and a third clock pulse during the low level period of the first clock pulse, and first and second latch circuits operated in response to the second and third clock pulses, respectively, of the clock pulse generator. The input terminal is connected through a resistor to the output of the first clock pulse. The input terminal is also connected to the inputs of the first and second latch circuits. The integrated circuit generates three kinds of outputs whose logical states correspond to different levels of three input signals, respectively, which are selectively supplied to said input terminal.
Inventors
- 👤 Tetsuo Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; G; G04; G04G; G04G5/00; G04G5/04; G04G5/043; H03K19/0002; H03K19/0175; H03K19/017545; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732; H03K5/00; H03K5/22; H03K5/24
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
An input integral circuit comprising one input terminal to which different levels of input signals are selectively supplied; a clock pulse generator having a first, a second and a third output from which a first, a second and a third clock pulse are generated respectively; a resistor connected between said input terminal and said first output of said clock pulse generator; and an output circuit portion at least including a first latch circuit having an input connected to said input terminal and a clock input connected to said second output of said clock pulse generator and a second latch circuit having an input connected to said input terminal and a clock input connected to said third output of said clock pulse generator, in which said output circuit portion generates outputs whose logical states correspond to different levels of input signals, respectively, which are selectively supplied to said input terminal.
Claim 2
Dependent Claim
149 words
An input integral circuit comprising one input terminal to which different levels of input signals are selectively supplied; a clock pulse generator having a first, a second and a third output from which a first, a second and a third clock pulse are generated respectively; a resistor connected between said input terminal and said first output of said clock pulse generator; and an output circuit portion at least including a first latch circuit having an input connected to said input terminal and a clock input connected to said second output of said clock pulse generator and a second latch circuit having an input connected to said input terminal and a clock input connected to said third output of said clock pulse generator, in which said output circuit portion generates outputs whose logical states correspond to different levels of input signals, respectively, which are selectively supplied to said input terminal.
Claim 3
Dependent Claim
72 words
An input integral circuit according to claim 1, in which said first, second and third clock pulses of said clock pulse generator are in such a relation that said second clock pulse is generated during a time period in which said first clock pulse is at a high level and that said third clock pulse is generated during a time period in which said first clock pulse is at a low level.
Claim 4
Dependent Claim
93 words
An input integral circuit according to claim 1, in which said output circuit portion further includes third and fourth latch circuits connected to said first and second latch circuits to which said second and third clock pulses are supplied, respectively, a NOR gate having inputs connected to outputs of said first and third latch circuits; and an AND gate having inputs connected to outputs of said second and fourth latch circuits, in which said third and fourth latch circuits are driven by said third and second clock pulses from said clock pulse generator.
Claim 5
Dependent Claim
27 words
An input integral circuit according to claim 3, in which said second and third clock pulses are generated in a manner to have a mutually different phase.
Claim 6
Dependent Claim
151 words
An input integral circuit comprising one input terminal to which three different levels of input signals are selectively supplied; a clock pulse generator having a first, a second and a third output from which a first, a second and a third clock pulse are generated respectively; a resistor connected between said input terminal and said first output of said clock pulse generator; and an output circuit portion at least including a first latch circuit having an input connected to said input terminal and a clock input connected to said second output of said clock generator and a second latch circuit having an input connected to said input terminal and a clock input connected to said third output of said pulse generator, in which said output circuit portion generates selectively outputs whose three logical states correspond to three different levels of input signals, respectively, which are selectively supplied to said input terminal.
Claim 7
Dependent Claim
151 words
An input integral circuit comprising one input terminal to which three different levels of input signals are selectively supplied; a clock pulse generator having a first, a second and a third output from which a first, a second and a third clock pulse are generated respectively; a resistor connected between said input terminal and said first output of said clock pulse generator; and an output circuit portion at least including a first latch circuit having an input connected to said input terminal and a clock input connected to said second output of said clock generator and a second latch circuit having an input connected to said input terminal and a clock input connected to said third output of said pulse generator, in which said output circuit portion generates selectively outputs whose three logical states correspond to three different levels of input signals, respectively, which are selectively supplied to said input terminal.
Claim 8
Dependent Claim
25 words
An input integral circuit according to claim 5 wherein said three different levels of input signals are "1" level, "float" level and "0" level, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-18 | 1982-03-20 | 1982-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-18 | 1986-03-20 | 1986-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-18 | 1990-03-20 | 1990-09-19 | $7700.00 | Window Closed / Lapsed |