Three-state discernment circuit

Claim 2

A three-state discernment circuit comprising: first signal generating means for generating a binary signal including logic 0 and 1 levels, said logic 0 and 1 levels being alternately generated in synchronism with a clock signal; means for applying said binary signal from said first signal generating means to one predetermined terminal through circuit means having a high output impedance, said predetermined terminal being adapted to be selectively connected to power source and ground potentials and opened therefrom; second signal generating means for receiving a first signal from said predetermined terminal to generate a second signal synchronous with said clock signal but delayed by one bit relative to said first signal; first logic means for receiving said first and second signals to produce a first logic output representative of an EXCLUSIVE OR combination thereof; second logic means for receiving said first logic output and one of said first and second signals to produce a second logic output representative of a NOR combination thereof; and third logic means for receiving said first logic output and an inversion of one of said first and second signals to produce a third logic output representative of a NOR combination thereof; whereby a desired signal is obtained from one of said first, second and third logic means in accordance with one of the condition that said predetermined terminal is connected to the power source potential, the condition that the predetermined terminal is connected to the ground potential and the condition that the predetermined terminal is opened from the power source and ground potentials.

Claim 3

A three-state discernment circuit comprising: first signal generating means for generating a binary signal including logic 0 and 1 levels, said logic 0 and 1 levels being alternately generated in synchronism with a clock signal; means for applying said binary signal from said first signal generating means to one predetermined terminal through circuit means having a high output impedance, said predetermined terminal being adapted to be selectively connected to power source and ground potentials and opened therefrom; second signal generating means for receiving a first signal from said predetermined terminal to generate a second signal synchronous with said clock signal but delayed by one bit relative to said first signal; first logic means for receiving said first and second signals to produce a first logic output representative of an EXCLUSIVE OR combination thereof; second logic means for receiving said first logic output and one of said first and second signals to produce a second logic output representative of a NOR combination thereof; and third logic means for receiving said first logic output and an inversion of one of said first and second signals to produce a third logic output representative of a NOR combination thereof; whereby, when said predetermined terminal is connected to the power source potential said first and second signals take a logic 1 level so that said first, second and third logic outputs take logic 0, 0 and 1 levels respectively, when said predetermined terminal is connected to the ground potential said first and second signals take a logic 0 level so that said first, second and third logic outputs take logic 0, 1 and 0 levels respectively, and when said predetermined terminal is opened from the power source and ground potentials said first and second signals take logic 0 and 1 levels alternately so that said first, second and third logic outputs take logic 1, 0 and 0 levels respectively.

Claim 4

A three-state discernment circuit comprising: first signal generating means for generating a binary signal including logic 0 and 1 levels, said logic 0 and 1 levels being alternately generated in synchronism with a clock signal; means for applying said binary signal from said first signal generating means to one predetermined terminal through circuit means having a high output impedance, said predetermined terminal being adapted to be selectively connected to power source and ground potentials and opened therefrom; second signal generating means for receiving a first signal from said predetermined terminal to generate a second signal synchronous with said clock signal but delayed by one bit relative to said first signal; first logic means for receiving said first and second signals to produce a first logic output representative of an EXCLUSIVE OR combination thereof; second logic means for receiving said first logic output and one of said first and second signals to produce a second logic output representative of a NOR combination thereof; and third logic means for receiving said first logic output and an inversion of one of said first and second signals to produce a third logic output representative of a NOR combination thereof; whereby, when said predetermined terminal is connected to the power source potential said first and second signals take a logic 1 level so that said first, second and third logic outputs take logic 0, 0 and 1 levels respectively, when said predetermined terminal is connected to the ground potential said first and second signals take a logic 0 level so that said first, second and third logic outputs take logic 0, 1 and 0 levels respectively, and when said predetermined terminal is opened from the power source and ground potentials said first and second signals take logic 0 and 1 levels alternately so that said first, second and third logic outputs take logic 1, 0 and 0 levels respectively.