Encoder circuit to reduce pin count for data entry into insulated gate field effect transistor integrated circuits

Claim 2

An encoder circuit for encoding a tri-state input data signal represented by the presence and absence of an input binary signal into three independent logic output voltages comprising: a. first circuit means operatively responsive only to positive input voltage having a first input terminal for receiving said input voltage, said first circuit means including a bipolar transistor having its emitter connected to said first input terminal for receiving said input voltage and its collector connected to said positive output terminal, b. second circuit means operatively responsive only to negative input voltage having a second input terminal for receiving said input voltage and having a negative output terminal, said second circuit means including a field effect transistor having its gate connected to said second input terminal for receiving said input voltage and its drain connected to said negative output terminal; and c. gating means connected to said output terminals of said first and second circuit means for providing said three output voltages.

Claim 3

The encoder circuit of claim 1 further including: a. first bias means for voltage biasing said collector terminal; and b. second bias means for voltage biasing said drain terminal.

Claim 4

The encoder circuit of claim 1 wherein said base terminal and said source terminal are connected to circuit ground.

Claim 5

The encoder circuit of claim 2 wherein said bias means are comprised of gate-shorted-to-drain field effect transistors.

Claim 6

An encoder circuit for generating a different binary combination of first and second output signals in response to each of three different voltage levels of a tri-level voltage signal applied to its input terminal comprised of: a. a field effect transistor having source, drain and gate terminals; b. a bipolar transistor having emitter, collectoR and base terminals; c. first conductive means electrically coupling said emitter terminal and said gate terminal to provide said input terminal; d. second conductive means electrically coupling said base terminal and said source terminal to circuit ground; e. first means for electrically coupling a base voltage to said collector terminal, said collector terminal providing means for generating said first binary ouput signal; and f. second means for electrically coupling a bias voltage to said drain terminal, said drain terminal providing means for generating said second binary output signal.

Claim 7

An encoder circuit for generating a different binary combination of first and second output signals in response to each of three different voltage levels of a tri-level voltage signal applied to its input terminal comprised of: a. a field effect transistor having source, drain and gate terminals; b. a bipolar transistor having emitter, collectoR and base terminals; c. first conductive means electrically coupling said emitter terminal and said gate terminal to provide said input terminal; d. second conductive means electrically coupling said base terminal and said source terminal to circuit ground; e. first means for electrically coupling a base voltage to said collector terminal, said collector terminal providing means for generating said first binary ouput signal; and f. second means for electrically coupling a bias voltage to said drain terminal, said drain terminal providing means for generating said second binary output signal.

Claim 8

The encoder circuit of claim 5 wherein said first and second means are comprised of gate-shorted-to-drain field effect transistors.

Claim 9

The encoder circuit of claim 5 including logic means coupled to said collector terminal and said drain terminal for generating three independent logid signals, each of said three independent logic signals corresponding to one of the three different binary combinations of said first and second output signals.

Claim 10

An integrated semiconductor encoder circuit for generating a different binary combination of first and second output signals in response to each Of three different voltage levels of a tri-level voltage signal applied to its input terminal comprised of: a. a monocrystalline semiconductor body having two major surfaces, said body including: i. a semiconductor substrate of one conductivity type, and ii. at least four regions of opposite conductivity type in said substrate extending to one of said major surfaces; b. a layer of insulating material adherently formed on said one major surface having thicker and thinner portions, a thinner portion being located between a first and second of said regions of opposite conductivity type and having openings in said thicker portion exposing areas of selected ones of said regions of opposite conductivity type including said first and second regions; c. an area of adherent metal formed on at least one thinner portion of said insulating layer to provide a gate terminal for a field effect transistor; d. metal adherently formed within said openings in said layer of insulating material ohmically connected to the exposed areas of said regions of opposite conductivity type to provide source and drain terminals to said first and second regions of opposite conductivity type for said field effect transistor and provide at least two additional terminals to third and fourth regions of opposite conductivity type for a bipolar transistor, said additional terminals being emitter and collector; e. a layer of metal adherently formed on the other major surface to provide a base terminal for said bipolar transistor; f. means for electrically connecting said emitter terminal and said gate terminal to provide said input terminal; g. means coupling said base terminal and said source terminal to circuit ground; h. first means for coupling a bias voltage to said collector terminal, said collector terminal providing means for generating said first binary output signal; and i. second means for coupling a bias voltage to said drain terminal, said drain terminal providing means for generating said second binary output signal.

Claim 11

An integrated semiconductor encoder circuit for generating a different binary combination of first and second output signals in response to each Of three different voltage levels of a tri-level voltage signal applied to its input terminal comprised of: a. a monocrystalline semiconductor body having two major surfaces, said body including: i. a semiconductor substrate of one conductivity type, and ii. at least four regions of opposite conductivity type in said substrate extending to one of said major surfaces; b. a layer of insulating material adherently formed on said one major surface having thicker and thinner portions, a thinner portion being located between a first and second of said regions of opposite conductivity type and having openings in said thicker portion exposing areas of selected ones of said regions of opposite conductivity type including said first and second regions; c. an area of adherent metal formed on at least one thinner portion of said insulating layer to provide a gate terminal for a field effect transistor; d. metal adherently formed within said openings in said layer of insulating material ohmically connected to the exposed areas of said regions of opposite conductivity type to provide source and drain terminals to said first and second regions of opposite conductivity type for said field effect transistor and provide at least two additional terminals to third and fourth regions of opposite conductivity type for a bipolar transistor, said additional terminals being emitter and collector; e. a layer of metal adherently formed on the other major surface to provide a base terminal for said bipolar transistor; f. means for electrically connecting said emitter terminal and said gate terminal to provide said input terminal; g. means coupling said base terminal and said source terminal to circuit ground; h. first means for coupling a bias voltage to said collector terminal, said collector terminal providing means for generating said first binary output signal; and i. second means for coupling a bias voltage to said drain terminal, said drain terminal providing means for generating said second binary output signal.

Claim 12

The integrated circuit of claim 8 including logic means coupled to said collector terminal and said drain terminal for generating three independent logic signals, each logic signal corresponding to one of the three different combinations of said first and second output signals.

Claim 13

The integrated circuit of claim 8 wherein said first and second means are comprised of field effect transistors formed on said semiconductor substrate and having respective source, drain and gate terminals, the gate terminals of each being electrically shorted to their respective drain terminals to provide means for applying said bias voltage and the source terminals of each providing means for connection to the circuit.