Patent US4988636A successfully refreshed from Google Patents.
US4988636A
Expired / Lapsed
US
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Method of making bit stack compatible input/output circuits
Assignee: International Business Machines Corp
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Filing: 1990-01-29
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Granted: 1991-01-29
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Expires: 2010-01-29
Abstract
Abstract In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other other forming row groups of said like subcomponents; and (4) forming at least one guard ring around the subcomponent row groups. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.
Inventors
- 👤 Robert P. Masleid
- 👤 Parsotam T. Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:04
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1078; H10D89/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
111 words
A method for positioning components of a plurality of input/output circuits on a semiconductor substrate containing circuits in addition to said input/output circuits, each input/output circuit for processing a single bit in a multiple bit group, said method comprising the steps of: (1) dividing each input/output circuit into groups containing similar function subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting said subcomponents to perform said function; (3) placing said columns adjacently to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming at least one guard ring around said subcomponent row group.
Claim 2
Independent Claim
111 words
A method for positioning components of a plurality of input/output circuits on a semiconductor substrate containing circuits in addition to said input/output circuits, each input/output circuit for processing a single bit in a multiple bit group, said method comprising the steps of: (1) dividing each input/output circuit into groups containing similar function subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting said subcomponents to perform said function; (3) placing said columns adjacently to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming at least one guard ring around said subcomponent row group.
Claim 3
Dependent Claim
23 words
A method according to claim 1 wherein step (1) includes dividing said subcomponents into driver, receiver or electrostatic discharge protection functional subcomponent groups.
Claim 4
Dependent Claim
25 words
A method according to claim 1 wherein step (2) includes placing said subcomponents in like positions relative to placement of like subcomponents in other columns.
Claim 5
Dependent Claim
21 words
A method according to claim 1 wherein step (3) includes packing said like subcomponents in close adjacency forming said row groups.
Claim 6
Dependent Claim
15 words
A method according to claim 1 wherein step (4) includes combining guard rings where appropriate.
Claim 7
Dependent Claim
32 words
A method according to claim 4 wherein step (3) further includes the placing of each of said columns according to a relative position of the input/output circuit's bit in the bit group.
Claim 8
Dependent Claim
26 words
A method according to claim 2 wherein the step of determining if electrostatic discharge protection circuits are required and, if not, removing any electrostatic discharge circuits.
Claim 9
Independent Claim
157 words
A method for positioning components of all input/output circuits on a semiconductor substrate containing other circuits in addition to said input/output circuits, each input/output circuit for processing a single bit in a multiple bit group, said method comprising the steps of: (1) separating input/output subcomponent circuit components from components of said other circuits; (2) dividing each input/output circuit into component groups wherein each group contains a plurality of subcomponents interconnected to perform a function; (3) forming vertical column portions of subcomponents for each input/output circuit and connecting said subcomponents to perform said function; (4) forming an input/output circuit column for each bit by placing said vertical column portions in vertical adjacentancy and connecting said column portions; (5) placing said vertical columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (6) forming at least one guard ring around said subcomponent row group.
Claim 10
Independent Claim
157 words
A method for positioning components of all input/output circuits on a semiconductor substrate containing other circuits in addition to said input/output circuits, each input/output circuit for processing a single bit in a multiple bit group, said method comprising the steps of: (1) separating input/output subcomponent circuit components from components of said other circuits; (2) dividing each input/output circuit into component groups wherein each group contains a plurality of subcomponents interconnected to perform a function; (3) forming vertical column portions of subcomponents for each input/output circuit and connecting said subcomponents to perform said function; (4) forming an input/output circuit column for each bit by placing said vertical column portions in vertical adjacentancy and connecting said column portions; (5) placing said vertical columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (6) forming at least one guard ring around said subcomponent row group.
Claim 11
Dependent Claim
23 words
A method according to claim 8 wherein step (2) includes dividing said subcomponents into driver, receiver or electrostatic discharge protection functional component groups.
Claim 12
Dependent Claim
26 words
A method according to claim 8 wherein step (3) includes placing said subcomponents in like positions relative to placement of like subcomponents in other column portions.
Claim 13
Dependent Claim
21 words
A method according to claim 8 wherein step (5) includes packing said like subcomponents in close adjacency forming said row groups.
Claim 14
Dependent Claim
15 words
A method according to claim 8 wherein step (6) includes combining guard rings where appropriate.
Claim 15
Dependent Claim
32 words
A method according to claim 11 wherein step (5) further includes the placing of each of said columns according to a relative position of the input/output circuit's bit in the bit group.
Claim 16
Dependent Claim
29 words
A method according to claim 9 wherein step (2) includes a step of determining if electrostatic discharge protection circuits are required and, if not, removing any electrostatic discharge circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |